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MRB—DTC Mode Register B
Bit
:
CHNE
Initial value
:
Undefined
Read/Write
:
DTC Chain Transfer Enable
CHNE
SAR—DTC Source Address Register
Bit
:
23
Initial value
:
Unde-
fined
Read/Write
:
7
6
5
DISEL
CHNS
Undefined
Undefined
DTC Interrupt Select
0
After DTC data transfer ends, the CPU interrupt
is disabled unless the transfer counter is 0
1
After DTC data transfer ends, the CPU interrupt
is enabled
CHNS
0
No chain transfer (At end of DTC data transfer, DTC waits
for activation)
1
0
Chain transfer every time
1
1
Chain transfer only when transfer counter = 0
22
21
20
19
Unde-
Unde-
Unde-
Unde-
fined
fined
fined
fined
Specifies DTC transfer data source address
H'F800—H'FBFF
4
3
Undefined
Undefined
Undefined
Reserved
Only 0 should be written to these bits
Description
H'F800—H'FBFF
- - -
- - -
- - -
- - -
Rev. 5.00, 12/03, page 943 of 1088
2
1
0
Undefined
Undefined
DTC Chain Transfer Select
4
3
2
1
Unde-
Unde-
Unde-
Unde-
fined
fined
fined
fined
DTC
DTC
0
Unde-
fined
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