Register Configuration - Renesas H8S/2319 series Hardware Manual

8.7.2

Register Configuration

Table 8-11 shows the port B register configuration.
Table 8-11 Port B Registers
Name
Port B data direction register
Port B data register
Port B register
Port B MOS pull-up control register
Note: * Lower 16 bits of the address.
Port B Data Direction Register (PBDDR)
Bit : 7
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Initial value : 0
R/W : W
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode. The OPE bit in SBYCR is used to select whether the address output pins
retain their output state or become high-impedance when a transition is made to software standby
mode.
• Modes 4 and 5
The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits.
• Mode 6 *
Setting PBDDR bits to 1 makes the corresponding port B pins address outputs, while clearing
the bits to 0 makes the pins input ports.
• Mode 7 *
Setting PBDDR bits to 1 makes the corresponding port B pins outputs, while clearing the bits
to 0 makes the pins input ports.
Note: * Modes 6 and 7 are not available in the ROMless versions.
Abbreviation
PBDDR
PBDR
PORTB
PBPCR
6 5
0 0
W W W
R/W Initial Value
W H'00
R/W H'00
R Undefined
R/W H'00
4 3 2
0 0 0
W W
Rev. 5.00, 12/03, page 255 of 1088
Address *
H'FEBA
H'FF6A
H'FF5A
H'FF71
1 0
0 0
W W