Renesas H8S/2319 series Hardware Manual page 974

DAR—DTC Destination Address Register
Bit : 23
Unde-
Initial value :
fined

Read/Write :
CRA—DTC Transfer Count Register A
Bit : 15
Initial value :
Unde-
fined

Read/Write :
CRB—DTC Transfer Count Register B
Bit :
15
Initial value :
Unde-
fined

Read/Write :
Rev. 5.00, 12/03, page 944 of 1088
22 21 20 19
Unde- Unde- Unde- Unde-
fined fined fined fined
   
Specifies DTC transfer data destination address
14 13 12 11
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
   
CRAH
Specifies the number of DTC data transfers
14 13 12 11
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
   
Specifies the number of DTC block data transfers
H'F800—H'FBFF
- - -
- - -
- - -
- - -
H'F800—H'FBFF
10 9 8 7 6
Unde- Unde- Unde- Unde-
fined fined fined fined
    
H'F800—H'FBFF
10 9 8 7 6
Unde- Unde- Unde- Unde-
fined fined fined fined
    
4 3 2
Unde- Unde- Unde- Unde-
fined fined fined fined
   
5 4 3 2
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
   
CRAL
5 4 3 2
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
    
DTC
1 0
Unde-
fined

DTC
1 0
Unde-
fined
 
DTC
1 0
Unde-
fined
