Renesas H8S/2319 series Hardware Manual page 313

Bus Control Register L (BCRL)
Bit : 7
BRLE
Initial value : 0
R/W : R/W
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, selection of the area partition unit, and enabling or disabling of WAIT pin input.
BCRL is initialized to H'3C by a reset, and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE Description
External bus release disabled. BREQ, BACK, and BREQO pins can be used as I/O
0
ports
1 External bus release enabled
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (BREQ) in the external bus-released state, or when an internal bus
master performs an external space access.
Bit 6
BREQOE Description
BREQO output disabled. BREQO pin can be used as I/O port
0
BREQO output enabled
1
Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT
pin.
Bit 0
WAITE Description
Wait input by WAIT pin disabled. WAIT pin can be used as I/O port
0
Wait input by WAIT pin enabled
1
6 5
BREQOE EAE
0 1
R/W R/W
4 3
— —
1 1
R/W R/W R/W
Rev. 5.00, 12/03, page 283 of 1088
2 1
— — WAITE
1 0
R/W R/W
(Initial value)
(Initial value)
(Initial value)
0
0