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Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a
number of data transfers can be performed consecutively in response to a single transfer request.
In data transfer with CHNE set to 1, determination of the end of the specified number of transfers,
clearing of the interrupt source flag, and clearing of DTCER are not performed.
When CHNE is set to 1, the chain transfer condition can be selected with the CHNS bit.
Bit 7
CHNE
Description
0
End of DTC data transfer (activation waiting state)
1
DTC chain transfer (new register information is read, then data is transferred)
Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are
disabled or enabled after a data transfer.
Bit 6
DISEL
Description
0
After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is
0 (the DTC clears the interrupt source flag of the activating interrupt to 0)
1
After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the
interrupt source flag of the activating interrupt to 0)
Bit 5—DTC Chain Transfer Select (CHNS): Specifies the chain transfer condition when CHNE
is 1.
Bit 7
Bit 5
CHNE
CHNS
0
–
1
0
1
1
Bits 4 to 0—Reserved: These bits have no effect on DTC operation in the chip and should always
be written with 0.
Rev. 5.00, 12/03, page 188 of 1088
Description
No chain transfer (DTC data transfer end, activation waiting state entered)
DTC chain transfer
Chain transfer only when transfer counter = 0
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