Renesas H8S/2319 series Hardware Manual page 458

12.2.5 Serial Mode Register (SMR)
Bit : 7
C/A
Initial value : 0
R/W : R/W
SMR is an 8-bit register used to set the SCI's serial transfer format and select the baud rate
generator clock source.
SMR can be read or written to by the CPU at all times.
SMR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
and module stop mode it retains its previous state.
Bit 7—Communication Mode (C/A A A A ): Selects asynchronous mode or synchronous mode as the
SCI operating mode.
Bit 7
C/A A A A
Description
0 Asynchronous mode
1 Synchronous mode
Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In
synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting.
Bit 6
CHR Description
0 8-bit data
7-bit data *
1
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible
to choose between LSB-first or MSB-first transfer.
Rev. 5.00, 12/03, page 428 of 1088
6 5
CHR PE
0 0
R/W R/W R/W
4 3
O/E STOP
0 0
R/W R/W
2 1
MP CKS1 CKS0
0 0
R/W R/W
(Initial value)
(Initial value)
0
0