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TMDR5—Timer Mode Register 5
7
Bit
:
Initial value
:
1
Read/Write
:
6
5
4
1
0
0
H'FEA1
3
2
1
MD3
MD2
MD1
0
0
0
R/W
R/W
R/W
Mode
0
0
0
1
1
0
1
×
×
1
Note: MD3 is a reserved bit. In a write, it
should always be written with 0.
Rev. 5.00, 12/03, page 959 of 1088
TPU5
0
MD0
0
R/W
0
Normal operation
1
Reserved
0
PWM mode 1
1
PWM mode 2
0
Phase counting mode 1
1
Phase counting mode 2
0
Phase counting mode 3
1
Phase counting mode 4
×
×
: Don't care
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