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TCR5—Timer Control Register 5
Bit
:
7
Initial value
:
0
Read/Write
:
Note: * Synchronous operation setting is performed by setting
Rev. 5.00, 12/03, page 958 of 1088
6
5
CCLR1
CCLR0
CKEG1
0
0
R/W
R/W
R/W
Clock Edge
0
1
Note: This setting is ignored when channel
Counter Clear
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input capture
1
0
TCNT cleared by TGRB compare match/input capture
1
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
the SYNC bit in TSYR to 1.
4
3
2
CKEG0
TPSC2
0
0
0
R/W
R/W
Time Prescaler
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Note:
This setting is ignored when channel 5 is in phase
counting mode.
0
Count at rising edge
1
Count at falling edge
Count at both edges
5 is in phase counting mode.
The internal clock edge selection is
valid when the input clock is φ/4 or
slower. This setting is ignored
if φ/1 or overflow/underflow on
another channel is selected as the
input clock.
H'FEA0
1
0
TPSC1
TPSC0
0
0
R/W
R/W
Internal clock: counts on φ/1
Internal clock: counts on φ/4
Internal clock: counts on φ/16
Internal clock: counts on φ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKC pin input
Internal clock: counts on φ/256
External clock: counts on TCLKD pin input
TPU5
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