Renesas H8S/2319 series Hardware Manual page 21

11.3.1 Operation in Watchdog Timer Mode ................................................................... 415
11.3.2 Operation in Interval Timer Mode ....................................................................... 417
11.3.3 Timing of Overflow Flag (OVF) Setting ............................................................. 417
11.3.4 Timing of Watchdog Timer Overflow Flag (WOVF) Setting.............................. 418
11.4 Interrupts ........................................................................................................................... 418
11.5 Usage Notes ...................................................................................................................... 418
11.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 418
11.5.2 Changing Value of CKS2 to CKS0...................................................................... 419
11.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 419
11.5.4 System Reset by WDTOVF Signal...................................................................... 420
11.5.5 Internal Reset in Watchdog Timer Mode............................................................. 420
Section 12 Serial Communication Interface (SCI)
12.1 Overview........................................................................................................................... 421
12.1.1 Features................................................................................................................ 421
12.1.2 Block Diagram..................................................................................................... 423
12.1.3 Pin Configuration................................................................................................. 424
12.1.4 Register Configuration......................................................................................... 425
12.2 Register Descriptions ........................................................................................................ 426
12.2.1 Receive Shift Register (RSR) .............................................................................. 426
12.2.2 Receive Data Register (RDR) .............................................................................. 426
12.2.3 Transmit Shift Register (TSR) ............................................................................. 427
12.2.4 Transmit Data Register (TDR)............................................................................. 427
12.2.5 Serial Mode Register (SMR)................................................................................ 428
12.2.6 Serial Control Register (SCR).............................................................................. 431
12.2.7 Serial Status Register (SSR) ................................................................................ 435
12.2.8 Bit Rate Register (BRR) ...................................................................................... 438
12.2.9 Smart Card Mode Register (SCMR) .................................................................... 446
12.2.10 Module Stop Control Register (MSTPCR) .......................................................... 448
12.3 Operation .......................................................................................................................... 449
12.3.1 Overview.............................................................................................................. 449
12.3.2 Operation in Asynchronous Mode ....................................................................... 451
12.3.3 Multiprocessor Communication Function............................................................ 462
12.3.4 Operation in Synchronous Mode ......................................................................... 470
12.4 SCI Interrupts.................................................................................................................... 479
12.5 Usage Notes ...................................................................................................................... 480
Section 13 Smart Card Interface
13.1 Overview........................................................................................................................... 487
13.1.1 Features................................................................................................................ 487
13.1.2 Block Diagram..................................................................................................... 488
13.1.3 Pin Configuration................................................................................................. 489
13.1.4 Register Configuration......................................................................................... 490
.................................................... 421
..................................................................................... 487
Rev. 5.00, 12/03, page xxi of xxx