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6.4.4
Basic Timing
8-Bit 2-State Access Space: Figure 6-6 shows the bus timing for an 8-bit 2-state access space.
When an 8-bit access space is accessed, the upper half (D
The LWR pin is fixed high. Wait states cannot be inserted.
Read
Write
Note: n = 0 to 7
Figure 6-6 Bus Timing for 8-Bit 2-State Access Space
Rev. 5.00, 12/03, page 160 of 1088
φ
Address bus
CSn
AS
RD
D
to D
15
8
D
to D
7
0
HWR
LWR
D
to D
15
8
D
to D
7
0
to D
) of the data bus is used.
15
8
Bus cycle
T
T
1
2
High
Valid
High impedance
Valid
Invalid
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