Renesas H8S/2319 series Hardware Manual page 401

Renesas 16-bit single-chip microcomputer
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TCFV Flag/TCFU Flag Setting Timing: Figure 9-44 shows the timing for setting of the TCFV
flag in TSR by overflow occurrence, and TCIV interrupt request signal timing.
Figure 9-45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and
TCIU interrupt request signal timing.
φ
TCNT input
clock
TCNT
(overflow)
Overflow
signal
TCFV flag
TCIV interrupt
φ
TCNT
input clock
TCNT
(underflow)
Underflow signal
TCFU flag
TCIU interrupt
H'FFFF
Figure 9-44 TCIV Interrupt Setting Timing
H'0000
Figure 9-45 TCIU Interrupt Setting Timing
H'0000
H'FFFF
Rev. 5.00, 12/03, page 371 of 1088

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