Renesas H8S/2319 series Hardware Manual page 970

Module Register
Port E Port E data direction register
Port E data register
Port E register
Port E MOS pull-up control register PEPCR
Port F Port F data direction register
Port F data register
Port F register
Port function control register 1
Port function control register 2
System control register
Port G Port G data direction register
Port G data register
Port G register
Port function control register 1
Port function control register 2
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written for flag clearing.
3. Registers in the DTC cannot be read or written to directly.
4. Located as register information in on-chip RAM addresses H'EBC0 to H'EFBF. Cannot
be located in external memory space. Do not clear the RAME bit in SYSCR to 0 when
using the DTC.
5. Determined by the MCU operating mode.
6. Bits used for pulse output cannot be written to.
7. Only 0 can be written to bits 7 to 5, to clear the flags.
8. For information on writing, see section 11.2.4, Notes on Register Access.
9. Only 0 can be written to bit 7, to clear the flag.
10. Flash memory registers selection is performed by means of the FLSHE bit in system
control register 2 (SYSCR2).
11. In modes in which the on-chip flash memory is disabled, a read will return H'00, and
writes are invalid. Writes are also disabled when the FWE bit in FLMCR1 is cleared to
0 (except for the H8S/2319 F-ZTAT).
12. In the H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-
ZTAT when a high level is input to the FWE pin, the initial value is H'80. In the
H8S/2319 F-ZTAT, the initial value is H'80.
13. In the H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-
ZTAT when a low level is input to the FWE pin, or if a high level is input but the SWE
bit in FLMCR1 is not set, these registers are initialized to H'00.
In the H8S/2319 F-ZTAT, the EB11 to EB0 bits are initialized to 0 when the SWE1 bit
is not set to 1, and the EB15 to EB12 bits are initialized to 0 when the SWE2 bit is not
set to 1.
Rev. 5.00, 12/03, page 940 of 1088
Abbreviation R/W
PEDDR W
PEDR R/W
PORTE R
R/W
PFDDR W
PFDR R/W
PORTF R
PFCR1 R/W
PFCR2 R/W
SYSCR R/W
PGDDR W
PGDR R/W
PORTG R
PFCR1 R/W
PFCR2 R/W
Initial Value Address *
H'00 H'FEBD
H'00 H'FF6D
Undefined H'FF5D
H'00 H'FF74
17
H'80/H'00 *
H'FEBE
H'00 H'FF6E
Undefined H'FF5E
H'0F H'FF45
H'30 H'FFAC
H'01 H'FF39
H'10/H'00 H'FEBF
17 18
* *
18
H'00 *
H'FF6F
18
Undefined *
H'FF5F
H'0F H'FF45
H'30 H'FFAC
1