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16-Bit 3-State Access Space: Figures 6-11 to 6-13 show bus timings for a 16-bit 3-state access
space. When a 16-bit access space is accessed , the upper half (D
for the even address, and the lower half (D
Wait states can be inserted.
Address bus
D
Read
D
Write
D
D
Note: n = 0 to 7
Figure 6-11 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)
T
φ
CSn
AS
RD
to D
15
8
to D
7
0
HWR
LWR
to D
15
8
to D
7
0
to D
) for the odd address.
7
0
Bus cycle
T
1
2
High
Valid
High impedance
to D
) of the data bus is used
15
8
T
3
Valid
Invalid
Rev. 5.00, 12/03, page 165 of 1088
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