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Table 7-10 Number of States Required for Each Execution Phase
Access To:
Bus width
Access states
Execution
Vector read
phase
Register
information
read/write
Byte data read
Word data read
Byte data write
Word data write
Internal operation S
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · S
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
Rev. 5.00, 12/03, page 208 of 1088
On-
On-
Chip
Chip
RAM
ROM
32
16
1
1
S
—
1
I
S
1
—
J
S
1
1
K
S
1
1
K
S
1
1
L
S
1
1
L
1
M
+ Σ (J · S
I
Internal I/O
Registers
External Devices
8
16
8
2
2
2
—
—
4
—
—
—
2
2
2
4
2
4
2
2
2
4
2
4
+ K · S
+ L · S
) + M · S
J
K
L
16
3
2
3
6+2m 2
3+m
—
—
—
3+m
2
3+m
6+2m 2
3+m
3+m
2
3+m
6+2m 2
3+m
M
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