Renesas H8S/2319 series Hardware Manual page 545

Renesas 16-bit single-chip microcomputer
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nth transfer frame
Ds
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
RDRF
PER
Figure 13-11 Retransfer Operation in SCI Receive Mode
• Retransfer operation when SCI is in transmit mode
Figure 13-12 illustrates the retransfer operation when the SCI is in transmit mode.
[6] If an error signal is sent back from the receiving end after transmission of one frame is
completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next
parity bit is sampled.
[7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality
is received.
[8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
[9] If an error signal is not sent back from the receiving end, transmission of one frame, including
a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE
bit in SCR is enabled at this time, a TXI interrupt request is generated.
If DTC data transfer by a TXI source is enabled, the next data can be written to TDR
automatically. When data is written to TDR by the DTC, the TDRE bit is automatically cleared
to 0.
nth transfer frame
Ds
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
TDRE
Transfer to TSR from TDR
TEND
FER/ERS
Figure 13-12 Retransfer Operation in SCI Transmit Mode
Retransferred frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
[2]
[1]
Retransferred frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer to TSR from TDR
[7]
[6]
Transfer
frame n+1
(DE)
Ds D0 D1 D2 D3 D4
[4]
[3]
Transfer
frame n+1
(DE)
Ds D0 D1 D2 D3 D4
Transfer to TSR
from TDR
[9]
[8]
Rev. 5.00, 12/03, page 515 of 1088

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