Table of Contents
Advertisement
14.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t
after the ADST bit is set to 1, then starts conversion. Figure 14-5 shows the A/D
D
conversion timing. Table 14-4 indicates the A/D conversion time.
As indicated in figure 14-5, the A/D conversion time includes t
length of t
varies depending on the timing of the write access to ADCSR. The total conversion
D
time therefore varies within the ranges indicated in table 14-4.
In scan mode, the values given in table 14-4 apply to the first conversion time. In the second and
subsequent conversions the conversion time is as shown in table 14-5.
φ
Address bus
Write signal
Input sampling
timing
ADF
Legend:
(1)
(2)
t
D
t
SPL
t
CONV
(1)
(2)
t
D
: ADCSR write cycle
: ADCSR address
: A/D conversion start delay
: Input sampling time
: A/D conversion time
Figure 14-5 A/D Conversion Timing
and the input sampling time. The
D
t
SPL
t
CONV
Rev. 5.00, 12/03, page 531 of 1088
Advertisement
Table of Contents
