Renesas H8S/2319 series Hardware Manual page 349

Bit 3 Bit 2
Channel IOC3 IOC2
0 0 0
1
1 0
1
Note: * When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Bit 1 Bit 0
IOC1 IOC0 Description
0 0 TGR0C
is output
1
compare
0
1
register *
1
0 0
1
1 0
1
0 0 TGR0C
is input
1
capture
×
1
register *
× ×
Output disabled
Initial output is 0 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
Output disabled
Initial output is 1 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Capture input Input capture at rising edge
source is
Input capture at falling edge
TIOCC0 pin
Input capture at both edges
Capture input Input capture at TCNT1
source is channel count-up/count-down
1/count clock
Rev. 5.00, 12/03, page 319 of 1088
(Initial value)
×: Don't care