Renesas H8S/2319 series Hardware Manual page 15

Section 4 Exception Handling
4.1 Overview........................................................................................................................... 99
4.1.1 Exception Handling Types and Priority............................................................... 99
4.1.2 Exception Handling Operation............................................................................. 99
4.1.3 Exception Vector Table ....................................................................................... 100
4.2 Reset ................................................................................................................................. 102
4.2.1 Overview.............................................................................................................. 102
4.2.2 Reset Sequence .................................................................................................... 102
4.2.3 Interrupts after Reset............................................................................................ 103
4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 103
4.3 Traces................................................................................................................................ 104
4.4 Interrupts ........................................................................................................................... 105
4.5 Trap Instruction................................................................................................................. 106
4.6 Stack Status after Exception Handling.............................................................................. 106
4.7 Notes on Use of the Stack ................................................................................................. 107
Section 5 Interrupt Controller
5.1 Overview........................................................................................................................... 109
5.1.1 Features................................................................................................................ 109
5.1.2 Block Diagram..................................................................................................... 110
5.1.3 Pin Configuration................................................................................................. 111
5.1.4 Register Configuration......................................................................................... 111
5.2 Register Descriptions ........................................................................................................ 112
5.2.1 System Control Register (SYSCR) ...................................................................... 112
5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 113
5.2.3 IRQ Enable Register (IER) .................................................................................. 114
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 115
5.2.5 IRQ Status Register (ISR).................................................................................... 116
5.3 Interrupt Sources ............................................................................................................... 117
5.3.1 External Interrupts ............................................................................................... 117
5.3.2 Internal Interrupts................................................................................................. 118
5.3.3 Interrupt Exception Vector Table ........................................................................ 118
5.4 Interrupt Operation............................................................................................................ 124
5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 124
5.4.2 Interrupt Control Mode 0 ..................................................................................... 127
5.4.3 Interrupt Control Mode 2 ..................................................................................... 129
5.4.4 Interrupt Exception Handling Sequence .............................................................. 131
5.4.5 Interrupt Response Times .................................................................................... 133
5.5 Usage Notes ...................................................................................................................... 134
5.5.1 Contention between Interrupt Generation and Disabling..................................... 134
5.5.2 Instructions that Disable Interrupts ...................................................................... 135
5.5.3 Times when Interrupts are Disabled .................................................................... 135
5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 135
......................................................................................... 99
.......................................................................................... 109
Rev. 5.00, 12/03, page xv of xxx