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10.6
Usage Notes
Note that the following kinds of contention can occur in the 8-bit timer module.
10.6.1
Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T
takes priority, so that the counter is cleared and the write is not performed.
Figure 10-10 shows this operation.
φ
Address
Internal write signal
Counter clear signal
TCNT
Figure 10-10 Contention between TCNT Write and Clear
Rev. 5.00, 12/03, page 400 of 1088
state of a TCNT write cycle, the clear
2
TCNT write cycle by CPU
T
T
1
TCNT address
N
2
H'00
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