Renesas H8S/2319 series Hardware Manual page 319

Port G Data Register (PGDR)
Bit : 7
—
Initial value : Undefined Undefined Undefined
R/W : —
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG4 to
PG0).
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
PGDR is initialized to H'00 (bits 4 to 0) by a reset, and in hardware standby mode. It retains its
prior state after in software standby mode.
Port G Register (PORTG)
Bit : 7
—
Initial value : Undefined Undefined Undefined
R/W : —
Note: * Determined by state of pins PG4 to PG0.
PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port G pins (PG4 to PG0) must always be performed on PGDR.
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G
read is performed while PGDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTG contents are determined by the pin states, as
PGDDR and PGDR are initialized. PORTG retains its prior state after in software standby mode.
6 5
— — PG4DR
— — R/W
6 5
— — PG4
— *
— —
4 3
PG3DR PG2DR
0 0
R/W R/W
4 3
PG3 PG2
— * — *
R R
Rev. 5.00, 12/03, page 289 of 1088
2 1
PG1DR PG0DR
0 0
R/W R/W
2 1
PG1 PG0
— * — *
R R
0
0
0
R