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7.8.2
Register Description
Table 7.12 summarizes the port 7 register. Port 7 is an input port, and port 7 has no data direction
register.
Table 7.12 Port 7 Data Register
Address*
Name
H'FFFD6
Port 7 data register
Note: * Lower 20 bits of the address in advanced mode.
Port 7 Data Register (P7DR)
Bit
Initial value
Read/Write
Note: *
Determined by pins P7 to P7 .
When port 7 is read, the pin logic levels are always read. P7DR cannot be modified.
7
6
P7
P7
7
6
—
*
—
*
R
R
7
0
Abbreviation
P7DR
5
4
P7
P7
5
4
—
*
—
*
R
R
R/W
Initial Value
R
Undetermined
3
2
P7
P7
3
2
—
*
—
*
R
R
1
0
P7
P7
1
0
—
*
—
*
R
R
185
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