Register Description; A/D Data Registers A To D (Addra To Addrd) - Hitachi H8/3672 Series Hardware Manual

14.3

Register Description

The A/D converter has the following registers. For details on register addresses, refer to appendix
B, Internal I/O Register.
• A/D data register A (ADDRA)
• A/D data register B (ADDRB)
• A/D data register C (ADDRC)
• A/D data register D (ADDRD)
• A/D control/status register (ADCSR)
• A/D control register (ADCR)
14.3.1

A/D Data Registers A to D (ADDRA to ADDRD)

There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are
shown in table 14-2.
The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.
The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. The
temporary register contents are transferred from the ADDR when the upper byte data is read.
When reading ADDR, read the upper bytes only or read in word units. ADDR is initialized to
H'0000.
Table 14-2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
AN0
AN1
AN2
AN3
Rev. 1.0, 03/01, page 196 of 280
A/D Data Register to Be Stored the Results of A/D Conversion
ADDRA
ADDRB
ADDRC
ADDRD