Hitachi H8/3008 Manuals

Manuals and User Guides for Hitachi H8/3008. We have 1 Hitachi H8/3008 manual available for free PDF download: Hardware Manual

Hitachi H8/3008 Hardware Manual (645 pages)

16-Bit Microcomputer

Brand: Hitachi | Category: Computer Hardware | Size: 2.06 MB

Table of Contents
5
Section 1 Overview

16
- Overview
  16
- Block Diagram
  21
- Pin Description
  22
  - Pin Arrangement
    22
  - Pin Functions
    25
  - Pin Assignments in each Mode
    29
Section 2 CPU

33
- Overview
  33
  - Features
    33
  - Differences from H8/300 CPU
    34
- CPU Operating Modes
  34
- Address Space
  35
- Register Configuration
  36
  - Overview
    36
  - General Registers
    37
  - Control Registers
    38
  - Initial CPU Register Values
    39
- Data Formats
  40
  - General Register Data Formats
    40
  - Memory Data Formats
    41
- Instruction Set
  43
- Addressing Modes and Effective Address Calculation
  57
  - Addressing Modes
    57
  - Effective Address Calculation
    59
- Processing States
  63
  - Overview
    63
  - Program Execution State
    63
  - Exception-Handling State
    64
  - Exception Handling Operation
    65
  - Bus-Released State
    66
  - Reset State
    66
  - Power-Down State
    67
- Basic Operational Timing
  67
Section 3 MCU Operating Modes

71
- Overview
  71
  - Operating Mode Selection
    71
  - Register Configuration
    72
- Mode Control Register (MDCR)
  72
- System Control Register (SYSCR)
  73
- Operating Mode Descriptions
  75
  - Mode 1
    75
  - Mode 2
    75
  - Mode 3
    75
  - Mode 4
    76
  - Modes 5 and 7
    76
- Pin Functions in each Operating Mode
  76
- Memory Map in each Operating Mode
  77
  - Reserved Areas
    77
Section 4 Exception Handling

79
- Overview
  79
- Reset
  82
  - Overview
    82
  - Reset Sequence
    82
  - Interrupts after Reset
    84
- Interrupts
  85
- Trap Instruction
  85
- Stack Status after Exception Handling
  86
- Notes on Stack Usage
  87
Section 5 Interrupt Controller

89
- Overview
  89
  - Features
    89
  - Block Diagram
    90
  - Pin Configuration
    91
  - Register Configuration
    91
- Register Descriptions
  91
- Interrupt Sources
  100
  - External Interrupts
    100
  - Internal Interrupts
    101
  - Interrupt Exception Handling Vector Table
    101
- Interrupt Operation
  105
  - Interrupt Handling Process
    105
  - Interrupt Exception Handling Sequence
    110
  - Interrupt Response Time
    111
- Usage Notes
  112
Section 6 Bus Controller

115
- Overview
  115
  - Features
    115
  - Block Diagram
    116
  - Pin Configuration
    117
  - Register Configuration
    118
- Register Descriptions
  118
- Operation
  129
  - Area Division
    129
  - Bus Specifications
    131
  - Memory Interfaces
    132
  - Chip Select Signals
    132
  - Address Output Method
    133
- Basic Bus Interface
  135
  - Overview
    135
  - Data Size and Data Alignment
    135
  - Valid Strobes
    136
  - Memory Areas
    137
  - Basic Bus Control Signal Timing
    138
  - Wait Control
    145
- Idle Cycle
  147
  - Operation
    147
  - Pin States in Idle Cycle
    149
- Bus Arbiter
  149
  - Operation
    150
- Register and Pin Input Timing
  152
  - Register Write Timing
    152
  - BREQ Pin Input Timing
    153
Section 7 I/O Ports

155
- Overview
  155
- Port 4
  158
  - Overview
    158
  - Register Descriptions
    159
- Port 6
  161
  - Overview
    161
  - 7.3.2 Register Descriptions
    161
- Port 7
  164
  - Overview
    164
  - Register Description
    164
- Port 8
  165
  - Overview
    165
  - Register Descriptions
    166
- Port 9
  169
  - Overview
    169
  - Register Descriptions
    169
- Port a
  172
  - Overview
    172
  - Register Descriptions
    173
- Port B
  182
  - Overview
    182
  - Register Descriptions
    183
Section 8 16-Bit Timer

187
- Overview
  187
  - Features
    187
  - Block Diagrams
    189
  - Pin Configuration
    192
  - Register Configuration
    193
- Register Descriptions
  194
- CPU Interface
  215
  - 16-Bit Accessible Registers
    215
  - 8-Bit Accessible Registers
    217
- Operation
  218
  - Overview
    218
  - Basic Functions
    218
  - Synchronization
    226
  - PWM Mode
    228
  - Phase Counting Mode
    232
  - 16-Bit Timer Output Timing
    234
- Interrupts
  235
  - Setting of Status Flags
    235
  - Timing of Clearing of Status Flags
    237
  - Interrupt Sources
    238
- Usage Notes
  239
Section 9 8-Bit Timers

251
- Overview
  251
  - Features
    251
  - Block Diagram
    253
  - Pin Configuration
    254
  - Register Configuration
    255
- Register Descriptions
  256
  - Timer Counters (8TCNT)
    256
  - Time Constant Registers a (TCORA)
    257
  - Time Constant Registers B (TCORB)
    258
  - Timer Control Register (8TCR)
    259
  - Timer Control/Status Registers (8TCSR)
    262
- CPU Interface
  267
  - 8-Bit Registers
    267
- Operation
  269
  - 8TCNT Count Timing
    269
  - Compare Match Timing
    270
  - Input Capture Signal Timing
    271
  - Timing of Status Flag Setting
    272
  - Operation with Cascaded Connection
    273
  - Input Capture Setting
    276
- Interrupt
  277
  - Interrupt Sources
    277
  - A/D Converter Activation
    278
- 8-Bit Timer Application Example
  278
- Usage Notes
  279
Section 10 Programmable Timing Pattern Controller (TPC)

289
- Overview
  289
  - Features
    289
  - Block Diagram
    290
  - Pin Configuration
    291
  - Register Configuration
    292
- Register Descriptions
  293
  - Port a Data Direction Register (PADDR)
    293
  - Port a Data Register (PADR)
    293
  - Port B Data Direction Register (PBDDR)
    294
  - Port B Data Register (PBDR)
    294
  - Next Data Register a (NDRA)
    295
  - Next Data Register B (NDRB)
    297
  - Next Data Enable Register a (NDERA)
    299
  - Next Data Enable Register B (NDERB)
    300
  - TPC Output Control Register (TPCR)
    301
  - TPC Output Mode Register (TPMR)
    303
- Operation
  305
  - Overview
    305
  - Output Timing
    306
  - Normal TPC Output
    307
  - Non-Overlapping TPC Output
    309
  - TPC Output Triggering by Input Capture
    311
- Usage Notes
  312
  - Operation of TPC Output Pins
    312
  - Note on Non-Overlapping Output
    312
Section 11 Watchdog Timer

315
- Overview
  315
  - Features
    315
  - Block Diagram
    316
  - Pin Configuration
    316
  - Register Configuration
    317
- Register Descriptions
  317
  - Timer Counter (TCNT)
    317
  - Timer Control/Status Register (TCSR)
    318
  - Reset Control/Status Register (RSTCSR)
    320
  - Notes on Register Access
    321
- Operation
  323
- Interrupts
  326
- Usage Notes
  326
Section 12 Serial Communication Interface

327
- Overview
  327
  - Features
    327
  - Block Diagram
    329
  - Pin Configuration
    330
  - Register Configuration
    331
- Register Descriptions
  332
  - Receive Shift Register (RSR)
    332
  - Receive Data Register (RDR)
    332
  - Transmit Shift Register (TSR)
    333
  - Transmit Data Register (TDR)
    333
  - Serial Mode Register (SMR)
    334
  - Serial Control Register (SCR)
    337
  - Serial Status Register (SSR)
    341
  - Bit Rate Register (BRR)
    346
- Operation
  354
  - Overview
    354
  - Operation in Asynchronous Mode
    357
  - Multiprocessor Communication
    366
  - Synchronous Operation
    373
- SCI Interrupts
  381
- Usage Notes
  382
  - Notes on Use of SCI
    382
Section 13 Smart Card Interface

387
- Overview
  387
  - Features
    387
  - Block Diagram
    388
  - Pin Configuration
    388
  - Register Configuration
    389
- Register Descriptions
  390
  - Smart Card Mode Register (SCMR)
    390
  - Serial Status Register (SSR)
    392
  - Serial Mode Register (SMR)
    393
  - Serial Control Register (SCR)
    394
- Operation
  395
  - Overview
    395
  - Pin Connections
    395
  - Data Format
    396
  - Register Settings
    398
  - Clock
    400
  - Transmitting and Receiving Data
    402
- Usage Notes
  409
Section 14 A/D Converter

413
- Overview
  413
  - Features
    413
  - Block Diagram
    414
  - Pin Configuration
    415
  - Register Configuration
    416
- Register Descriptions
  416
- CPU Interface
  420
- Operation
  422
  - Single Mode (SCAN = 0)
    422
  - Scan Mode (SCAN = 1)
    424
  - Input Sampling and A/D Conversion Time
    426
  - External Trigger Input Timing
    427
- Interrupts
  428
- Usage Notes
  428
Section 15 D/A Converter

433
- Overview
  433
  - Features
    433
  - Block Diagram
    434
  - Pin Configuration
    435
  - Register Configuration
    435
- Register Descriptions
  436
- Operation
  438
- D/A Output Control
  440
Section 16 RAM

441
- Overview
  441
  - Block Diagram
    442
  - Register Configuration
    442
- System Control Register (SYSCR)
  443
- Operation
  444
Section 17 Clock Pulse Generator

445
- Overview
  445
  - Block Diagram
    445
- Oscillator Circuit
  446
  - Connecting a Crystal Resonator
    446
  - External Clock Input
    448
- Duty Adjustment Circuit
  450
- Prescalers
  450
- Frequency Divider
  450
  - Register Configuration
    451
  - Division Control Register (DIVCR)
    451
  - Usage Notes
    452
Section 18 Power-Down State

453
- Overview
  453
- Register Configuration
  455
- Sleep Mode
  460
  - Transition to Sleep Mode
    460
  - Exit from Sleep Mode
    460
- Software Standby Mode
  460
- Hardware Standby Mode
  464
- Module Standby Function
  465
  - Module Standby Timing
    465
  - Read/Write in Module Standby
    465
  - Usage Notes
    465
- System Clock Output Disabling Function
  466
Section 19 Electrical Characteristics - Preliminary

467
- Absolute Maximum Ratings
  467
- DC Characteristics
  468
- AC Characteristics
  478
- A/D Conversion Characteristics
  484
- D/A Conversion Characteristics
  486
- Operational Timing
  487
  - Clock Timing
    487
  - Control Signal Timing
    488
  - Bus Timing
    490
  - TPC and I/O Port Timing
    494
  - Timer Input/Output Timing
    494
  - SCI Input/Output Timing
    495
Appendix A Instruction Set

497
- Instruction List
  497
  - Data Transfer Instructions
    499
  - Arithmetic Instructions
    501
  - Bit Manipulation Instructions
    506
- Operation Code Maps
  512
- Number of States Required for Execution
  515
Appendix B Internal I/O Registers

524
- Address List
  524
- Functions
  539
- B.2 Functions
  539
Appendix C I/O Port Block Diagrams

603
- Port 4 Block Diagram
  603
- Port 6 Block Diagrams
  604
- Port 7 Block Diagrams
  608
- Port 8 Block Diagrams
  609
- Port 9 Block Diagrams
  613
- Port a Block Diagrams
  619
- Port B Block Diagrams
  622
Appendix D Pin States

628
- Port States in each Mode
  628
- Pin States at Reset
  631
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode

633
Appendix F Product Code Lineup

634
Appendix G Package Dimensions

635
Appendix H Comparison of H8/300H Series Product Specifications

638
- Differences between H8/3067 and H8/3062 Series, H8/3048 Series, H8/3006 and H8/3007, and H8/3008
  638
- Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B)
  641

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Hitachi H8/3008 Manuals

Hitachi H8/3008 Hardware Manual (645 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller

Section 7 I/O Ports

Section 8 16-Bit Timer

Section 9 8-Bit Timers

Section 10 Programmable Timing Pattern Controller (TPC)

Section 11 Watchdog Timer

Section 12 Serial Communication Interface

Section 13 Smart Card Interface

Section 14 A/D Converter

Section 15 D/A Converter

Section 16 RAM

Section 17 Clock Pulse Generator

Section 18 Power-Down State

Section 19 Electrical Characteristics - Preliminary

Appendix A Instruction Set

Appendix B Internal I/O Registers

Appendix C I/O Port Block Diagrams

Appendix D Pin States

Appendix E Timing of Transition to and Recovery from Hardware Standby Mode

Appendix F Product Code Lineup

Appendix G Package Dimensions

Appendix H Comparison of H8/300H Series Product Specifications

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