Hitachi H8/3008 Manuals

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Hitachi H8/3008 Hardware Manual

Hitachi H8/3008 Hardware Manual (645 pages)

16-Bit Microcomputer  
Brand: Hitachi | Category: Computer Hardware | Size: 2.06 MB
Table of contents
Table Of Contents5................................................................................................................................................................
Section 1 Overview16................................................................................................................................................................
Block Diagram21................................................................................................................................................................
Pin Description22................................................................................................................................................................
Pin Functions25................................................................................................................................................................
Pin Assignments In Each Mode29................................................................................................................................................................
Section 2 Cpu33................................................................................................................................................................
Differences From H8/300 Cpu34................................................................................................................................................................
Address Space35................................................................................................................................................................
Register Configuration36................................................................................................................................................................
General Registers37................................................................................................................................................................
Control Registers38................................................................................................................................................................
Initial Cpu Register Values39................................................................................................................................................................
Data Formats40................................................................................................................................................................
Memory Data Formats41................................................................................................................................................................
Instruction Set43................................................................................................................................................................
Instructions And Addressing Modes44................................................................................................................................................................
Tables Of Instructions Classified By Function45................................................................................................................................................................
Basic Instruction Formats54................................................................................................................................................................
Notes On Use Of Bit Manipulation Instructions55................................................................................................................................................................
Addressing Modes And Effective Address Calculation57................................................................................................................................................................
Effective Address Calculation59................................................................................................................................................................
Processing States63................................................................................................................................................................
Exception-handling State64................................................................................................................................................................
Exception Handling Operation65................................................................................................................................................................
Bus-released State66................................................................................................................................................................
Power-down State67................................................................................................................................................................
On-chip Supporting Module Access Timing68................................................................................................................................................................
Access To External Address Space69................................................................................................................................................................
Section 3 Mcu Operating Modes71................................................................................................................................................................
System Control Register (syscr)73................................................................................................................................................................
Operating Mode Descriptions75................................................................................................................................................................
Mode 476................................................................................................................................................................
Memory Map In Each Operating Mode77................................................................................................................................................................
Section 4 Exception Handling79................................................................................................................................................................
Exception Vector Table80................................................................................................................................................................
Reset82................................................................................................................................................................
Interrupts After Reset84................................................................................................................................................................
Interrupts85................................................................................................................................................................
Stack Status After Exception Handling86................................................................................................................................................................
Notes On Stack Usage87................................................................................................................................................................
Section 5 Interrupt Controller89................................................................................................................................................................
Pin Configuration91................................................................................................................................................................
Interrupt Priority Registers A And B (ipra, Iprb)92................................................................................................................................................................
Irq Status Register (isr)97................................................................................................................................................................
Irq Enable Register (ier)98................................................................................................................................................................
Irq Sense Control Register (iscr)99................................................................................................................................................................
Interrupt Sources100................................................................................................................................................................
Internal Interrupts101................................................................................................................................................................
Interrupt Operation105................................................................................................................................................................
Interrupt Exception Handling Sequence110................................................................................................................................................................
Interrupt Response Time111................................................................................................................................................................
Usage Notes112................................................................................................................................................................
Instructions That Inhibit Interrupts113................................................................................................................................................................
Section 6 Bus Controller115................................................................................................................................................................
Access State Control Register (astcr)119................................................................................................................................................................
Wait Control Registers H And L (wcrh, Wcrl)120................................................................................................................................................................
Bus Release Control Register (brcr)124................................................................................................................................................................
Bus Control Register (bcr)125................................................................................................................................................................
Chip Select Control Register (cscr)127................................................................................................................................................................
Address Control Register (adrcr)128................................................................................................................................................................
Area Division129................................................................................................................................................................
Bus Specifications131................................................................................................................................................................
Memory Interfaces132................................................................................................................................................................
Address Output Method133................................................................................................................................................................
Basic Bus Interface135................................................................................................................................................................
Valid Strobes136................................................................................................................................................................
Memory Areas137................................................................................................................................................................
Basic Bus Control Signal Timing138................................................................................................................................................................
Wait Control145................................................................................................................................................................
Idle Cycle147................................................................................................................................................................
Pin States In Idle Cycle149................................................................................................................................................................
Operation150................................................................................................................................................................
Register And Pin Input Timing152................................................................................................................................................................
Breq Pin Input Timing153................................................................................................................................................................
Section 7 I/o Ports155................................................................................................................................................................
Port158................................................................................................................................................................
Register Descriptions159................................................................................................................................................................
Overview172................................................................................................................................................................
Section 8 16-bit Timer187................................................................................................................................................................
Block Diagrams189................................................................................................................................................................
Timer Synchro Register (tsnc)195................................................................................................................................................................
Timer Mode Register (tmdr)196................................................................................................................................................................
Timer Interrupt Status Register A (tisra)199................................................................................................................................................................
Timer Interrupt Status Register B (tisrb)202................................................................................................................................................................
Timer Interrupt Status Register C (tisrc)205................................................................................................................................................................
Timer Counters (16tcnt)207................................................................................................................................................................
General Registers (gra, Grb)208................................................................................................................................................................
Timer Control Registers (16tcr)209................................................................................................................................................................
Timer I/o Control Register (tior)211................................................................................................................................................................
Timer Output Level Setting Register C (tolr)213................................................................................................................................................................
Cpu Interface215................................................................................................................................................................
Bit Accessible Registers217................................................................................................................................................................
Synchronization226................................................................................................................................................................
Pwm Mode228................................................................................................................................................................
Phase Counting Mode232................................................................................................................................................................
Bit Timer Output Timing234................................................................................................................................................................
Timing Of Clearing Of Status Flags237................................................................................................................................................................
Section 9 8-bit Timers251................................................................................................................................................................
Time Constant Registers A (tcora)257................................................................................................................................................................
Time Constant Registers B (tcorb)258................................................................................................................................................................
Timer Control Register (8tcr)259................................................................................................................................................................
Timer Control/status Registers (8tcsr)262................................................................................................................................................................
Compare Match Timing270................................................................................................................................................................
Input Capture Signal Timing271................................................................................................................................................................
Timing Of Status Flag Setting272................................................................................................................................................................
Operation With Cascaded Connection273................................................................................................................................................................
Input Capture Setting276................................................................................................................................................................
Interrupt277................................................................................................................................................................
A/d Converter Activation278................................................................................................................................................................
Contention Between 8tcnt Write And Increment280................................................................................................................................................................
Contention Between Tcor Write And Compare Match281................................................................................................................................................................
Contention Between Tcor Read And Input Capture282................................................................................................................................................................
Contention Between Counter Clearing By Input Capture And Counter Increment283................................................................................................................................................................
Contention Between Tcor Write And Input Capture284................................................................................................................................................................
Contention Between Compare Matches A And B286................................................................................................................................................................
Section 10 Programmable Timing Pattern Controller (tpc)289................................................................................................................................................................
Port B Data Direction Register (pbddr)294................................................................................................................................................................
Next Data Register A (ndra)295................................................................................................................................................................
Next Data Register B (ndrb)297................................................................................................................................................................
Next Data Enable Register A (ndera)299................................................................................................................................................................
Next Data Enable Register B (nderb)300................................................................................................................................................................
Tpc Output Control Register (tpcr)301................................................................................................................................................................
Tpc Output Mode Register (tpmr)303................................................................................................................................................................
Output Timing306................................................................................................................................................................
Normal Tpc Output307................................................................................................................................................................
Non-overlapping Tpc Output309................................................................................................................................................................
Tpc Output Triggering By Input Capture311................................................................................................................................................................
Section 11 Watchdog Timer315................................................................................................................................................................
Timer Control/status Register (tcsr)318................................................................................................................................................................
Reset Control/status Register (rstcsr)320................................................................................................................................................................
Notes On Register Access321................................................................................................................................................................
Interval Timer Operation324................................................................................................................................................................
Timing Of Setting Of Watchdog Timer Reset Bit (wrst)325................................................................................................................................................................
Section 12 Serial Communication Interface327................................................................................................................................................................
Transmit Shift Register (tsr)333................................................................................................................................................................
Serial Mode Register (smr)334................................................................................................................................................................
Serial Control Register (scr)337................................................................................................................................................................
Serial Status Register (ssr)341................................................................................................................................................................
Bit Rate Register (brr)346................................................................................................................................................................
Operation In Asynchronous Mode357................................................................................................................................................................
Multiprocessor Communication366................................................................................................................................................................
Synchronous Operation373................................................................................................................................................................
Sci Interrupts381................................................................................................................................................................
Section 13 Smart Card Interface387................................................................................................................................................................
Data Format396................................................................................................................................................................
Register Settings398................................................................................................................................................................
Clock400................................................................................................................................................................
Transmitting And Receiving Data402................................................................................................................................................................
Section 14 A/d Converter413................................................................................................................................................................
A/d Control/status Register (adcsr)417................................................................................................................................................................
A/d Control Register (adcr)419................................................................................................................................................................
Scan Mode (scan = 1)424................................................................................................................................................................
Input Sampling And A/d Conversion Time426................................................................................................................................................................
External Trigger Input Timing427................................................................................................................................................................
Section 15 D/a Converter433................................................................................................................................................................
D/a Standby Control Register (dastcr)438................................................................................................................................................................
D/a Output Control440................................................................................................................................................................
Section 16 Ram441................................................................................................................................................................
Section 17 Clock Pulse Generator445................................................................................................................................................................
Oscillator Circuit446................................................................................................................................................................
External Clock Input448................................................................................................................................................................
Duty Adjustment Circuit450................................................................................................................................................................
Section 18 Power-down State453................................................................................................................................................................
Module Standby Control Register H (mstcrh)457................................................................................................................................................................
Module Standby Control Register L (mstcrl)458................................................................................................................................................................
Sleep Mode460................................................................................................................................................................
Exit From Software Standby Mode461................................................................................................................................................................
Sample Application Of Software Standby Mode463................................................................................................................................................................
Hardware Standby Mode464................................................................................................................................................................
Module Standby Function465................................................................................................................................................................
System Clock Output Disabling Function466................................................................................................................................................................
Absolute Maximum Ratings467................................................................................................................................................................
Dc Characteristics468................................................................................................................................................................
Ac Characteristics478................................................................................................................................................................
A/d Conversion Characteristics484................................................................................................................................................................
D/a Conversion Characteristics486................................................................................................................................................................
Operational Timing487................................................................................................................................................................
Control Signal Timing488................................................................................................................................................................
Bus Timing490................................................................................................................................................................
Tpc And I/o Port Timing494................................................................................................................................................................
Sci Input/output Timing495................................................................................................................................................................
Appendix A Instruction Set497................................................................................................................................................................
Data Transfer Instructions499................................................................................................................................................................
Arithmetic Instructions501................................................................................................................................................................
Bit Manipulation Instructions506................................................................................................................................................................
A.2 Operation Code Maps512................................................................................................................................................................
A.3 Number Of States Required For Execution515................................................................................................................................................................
Appendix B Internal I/o Registers524................................................................................................................................................................
B.2 Functions539................................................................................................................................................................
Appendix C I/o Port Block Diagrams603................................................................................................................................................................
C.2 Port 6 Block Diagrams604................................................................................................................................................................
C.3 Port 7 Block Diagrams608................................................................................................................................................................
C.4 Port 8 Block Diagrams609................................................................................................................................................................
C.5 Port 9 Block Diagrams613................................................................................................................................................................
C.6 Port A Block Diagrams619................................................................................................................................................................
C.7 Port B Block Diagrams622................................................................................................................................................................
Appendix D Pin States628................................................................................................................................................................
D.2 Pin States At Reset631................................................................................................................................................................
Appendix F Product Code Lineup634................................................................................................................................................................
Appendix G Package Dimensions635................................................................................................................................................................
H.1 Differences Between H8/3067 And H8/3062 Series, H8/3048 Series H8/3006 And H8/3007, And H8/3008638................................................................................................................................................................
H.2 Comparison Of Pin Functions Of 100-pin Package Products (fp-100b, Tfp-100b)641................................................................................................................................................................

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