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Hitachi H8/3008 Manuals
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Hitachi H8/3008 manual available for free PDF download: Hardware Manual
Hitachi H8/3008 Hardware Manual (645 pages)
16-Bit Microcomputer
Brand:
Hitachi
| Category:
Computer Hardware
| Size: 2.06 MB
Table of Contents
5
Table of Contents
16
Section 1 Overview
16
Overview
21
Block Diagram
22
Pin Description
22
Pin Arrangement
25
Pin Functions
29
Pin Assignments in Each Mode
33
Section 2 CPU
33
Overview
33
Features
34
Differences From H8/300 CPU
34
CPU Operating Modes
35
Address Space
36
Register Configuration
36
Overview
37
General Registers
38
Control Registers
39
Initial CPU Register Values
40
Data Formats
40
General Register Data Formats
41
Memory Data Formats
43
Instruction Set
43
Instruction Set Overview
44
Instructions and Addressing Modes
45
Tables of Instructions Classified By Function
54
2.6.4 Basic Instruction Formats
55
Notes On Use of Bit Manipulation Instructions
57
Addressing Modes and Effective Address Calculation
57
Addressing Modes
59
Effective Address Calculation
63
Processing States
63
Overview
63
Program Execution State
64
Exception-Handling State
65
Exception Handling Operation
66
Bus-Released State
66
Reset State
67
Power-Down State
67
Basic Operational Timing
67
Overview
67
On-Chip Memory Access Timing
68
On-Chip Supporting Module Access Timing
69
Access to External Address Space
71
Section 3 MCU Operating Modes
71
Overview
71
Operating Mode Selection
72
Register Configuration
72
Mode Control Register (MDCR)
73
System Control Register (SYSCR)
75
Operating Mode Descriptions
75
Mode 1
75
Mode 2
75
Mode 3
76
Mode 4
76
Modes 5 and 7
76
Pin Functions in Each Operating Mode
77
Memory Map in Each Operating Mode
77
Reserved Areas
79
Section 4 Exception Handling
79
Overview
79
Exception Handling Types and Priority
79
Exception Handling Operation
80
Exception Vector Table
82
Reset
82
Overview
82
Reset Sequence
84
Interrupts After Reset
85
Interrupts
85
Trap Instruction
86
Stack Status After Exception Handling
87
Notes On Stack Usage
89
Section 5 Interrupt Controller
89
Overview
89
Features
90
Block Diagram
91
Pin Configuration
91
Register Configuration
91
Register Descriptions
91
System Control Register (SYSCR)
92
Interrupt Priority Registers a and B (IPRA, IPRB)
97
IRQ Status Register (ISR)
98
IRQ Enable Register (IER)
99
IRQ Sense Control Register (ISCR)
100
Interrupt Sources
100
External Interrupts
101
Internal Interrupts
101
Interrupt Exception Handling Vector Table
105
Interrupt Operation
105
Interrupt Handling Process
110
Interrupt Exception Handling Sequence
111
Interrupt Response Time
112
Usage Notes
112
Contention Between Interrupt and Interrupt-Disabling Instruction
113
Instructions That Inhibit Interrupts
113
Interrupts During EEPMOV Instruction Execution
115
Section 6 Bus Controller
115
Overview
115
Features
116
Block Diagram
117
Pin Configuration
118
Register Configuration
118
Register Descriptions
118
Bus Width Control Register (ABWCR)
119
Access State Control Register (ASTCR)
120
Wait Control Registers H and L (WCRH, WCRL)
124
Bus Release Control Register (BRCR)
125
Bus Control Register (BCR)
127
Chip Select Control Register (CSCR)
128
Address Control Register (ADRCR)
129
Operation
129
Area Division
131
Bus Specifications
132
Memory Interfaces
132
Chip Select Signals
133
Address Output Method
135
Basic Bus Interface
135
Overview
135
Data Size and Data Alignment
136
Valid Strobes
137
Memory Areas
138
Basic Bus Control Signal Timing
145
Wait Control
147
Idle Cycle
147
Operation
149
Pin States in Idle Cycle
149
Bus Arbiter
150
Operation
152
Register and Pin Input Timing
152
Register Write Timing
153
BREQ Pin Input Timing
155
Section 7 I/O Ports
155
Overview
158
Port 4
158
Overview
159
Register Descriptions
161
Port 6
161
Overview
161
7.3.2 Register Descriptions
164
Port 7
164
Overview
164
Register Description
165
Port 8
165
Overview
166
Register Descriptions
169
Port 9
169
Overview
169
Register Descriptions
172
Port a
172
Overview
173
Register Descriptions
182
Port B
182
Overview
183
Register Descriptions
187
Section 8 16-Bit Timer
187
Overview
187
Features
189
Block Diagrams
192
Pin Configuration
193
Register Configuration
194
Register Descriptions
194
Timer Start Register (TSTR)
195
Timer Synchro Register (TSNC)
196
Timer Mode Register (TMDR)
199
Timer Interrupt Status Register a (TISRA)
202
Timer Interrupt Status Register B (TISRB)
205
Timer Interrupt Status Register C (TISRC)
207
Timer Counters (16TCNT)
208
General Registers (GRA, GRB)
209
Timer Control Registers (16TCR)
211
Timer I/O Control Register (TIOR)
213
Timer Output Level Setting Register C (TOLR)
215
CPU Interface
215
16-Bit Accessible Registers
217
8-Bit Accessible Registers
218
Operation
218
Overview
218
Basic Functions
226
Synchronization
228
PWM Mode
232
Phase Counting Mode
234
16-Bit Timer Output Timing
235
Interrupts
235
Setting of Status Flags
237
Timing of Clearing of Status Flags
238
Interrupt Sources
239
Usage Notes
251
Section 9 8-Bit Timers
251
Overview
251
Features
253
Block Diagram
254
Pin Configuration
255
Register Configuration
256
Register Descriptions
256
Timer Counters (8TCNT)
257
Time Constant Registers a (TCORA)
258
Time Constant Registers B (TCORB)
259
Timer Control Register (8TCR)
262
Timer Control/Status Registers (8TCSR)
267
CPU Interface
267
8-Bit Registers
269
Operation
269
8TCNT Count Timing
270
Compare Match Timing
271
Input Capture Signal Timing
272
Timing of Status Flag Setting
273
Operation with Cascaded Connection
276
Input Capture Setting
277
Interrupt
277
Interrupt Sources
278
A/D Converter Activation
278
8-Bit Timer Application Example
279
Usage Notes
279
Contention Between 8TCNT Write and Clear
280
Contention Between 8TCNT Write and Increment
281
Contention Between TCOR Write and Compare Match
282
Contention Between TCOR Read and Input Capture
283
Contention Between Counter Clearing By Input Capture and Counter Increment
284
Contention Between TCOR Write and Input Capture
285
Contention Between 8TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection)
286
Contention Between Compare Matches a and B
286
8TCNT Operation and Internal Clock Source Switchover
289
Section 10 Programmable Timing Pattern Controller (TPC)
289
Overview
289
Features
290
Block Diagram
291
Pin Configuration
292
Register Configuration
293
Register Descriptions
293
Port a Data Direction Register (PADDR)
293
Port a Data Register (PADR)
294
Port B Data Direction Register (PBDDR)
294
Port B Data Register (PBDR)
295
Next Data Register a (NDRA)
297
Next Data Register B (NDRB)
299
Next Data Enable Register a (NDERA)
300
Next Data Enable Register B (NDERB)
301
TPC Output Control Register (TPCR)
303
TPC Output Mode Register (TPMR)
305
Operation
305
Overview
306
Output Timing
307
Normal TPC Output
309
Non-Overlapping TPC Output
311
TPC Output Triggering By Input Capture
312
Usage Notes
312
Operation of TPC Output Pins
312
Note On Non-Overlapping Output
315
Section 11 Watchdog Timer
315
Overview
315
Features
316
Block Diagram
316
Pin Configuration
317
Register Configuration
317
Register Descriptions
317
Timer Counter (TCNT)
318
Timer Control/Status Register (TCSR)
320
Reset Control/Status Register (RSTCSR)
321
Notes On Register Access
323
Operation
323
Watchdog Timer Operation
324
Interval Timer Operation
324
Timing of Setting of Overflow Flag (OVF)
325
Timing of Setting of Watchdog Timer Reset Bit (WRST)
326
Interrupts
326
Usage Notes
327
Section 12 Serial Communication Interface
327
Overview
327
Features
329
Block Diagram
330
Pin Configuration
331
Register Configuration
332
Register Descriptions
332
Receive Shift Register (RSR)
332
Receive Data Register (RDR)
333
Transmit Shift Register (TSR)
333
Transmit Data Register (TDR)
334
Serial Mode Register (SMR)
337
Serial Control Register (SCR)
341
Serial Status Register (SSR)
346
Bit Rate Register (BRR)
354
Operation
354
Overview
357
Operation in Asynchronous Mode
366
Multiprocessor Communication
373
Synchronous Operation
381
SCI Interrupts
382
Usage Notes
382
Notes On Use of SCI
387
Section 13 Smart Card Interface
387
Overview
387
Features
388
Block Diagram
388
Pin Configuration
389
Register Configuration
390
Register Descriptions
390
Smart Card Mode Register (SCMR)
392
Serial Status Register (SSR)
393
Serial Mode Register (SMR)
394
Serial Control Register (SCR)
395
Operation
395
Overview
395
Pin Connections
396
Data Format
398
Register Settings
400
Clock
402
Transmitting and Receiving Data
409
Usage Notes
413
Section 14 A/D Converter
413
Overview
413
Features
414
Block Diagram
415
Pin Configuration
416
Register Configuration
416
Register Descriptions
416
A/D Data Registers a to D (ADDRA to ADDRD)
417
A/D Control/Status Register (ADCSR)
419
A/D Control Register (ADCR)
420
CPU Interface
422
Operation
422
Single Mode (SCAN = 0)
424
Scan Mode (SCAN = 1)
426
Input Sampling and A/D Conversion Time
427
External Trigger Input Timing
428
Interrupts
428
Usage Notes
433
Section 15 D/A Converter
433
Overview
433
Features
434
Block Diagram
435
Pin Configuration
435
Register Configuration
436
Register Descriptions
436
D/A Data Registers 0 and 1 (DADR0, DADR1)
436
D/A Control Register (DACR)
438
D/A Standby Control Register (DASTCR)
438
Operation
440
D/A Output Control
441
Section 16 RAM
441
Overview
442
Block Diagram
442
Register Configuration
443
System Control Register (SYSCR)
444
Operation
445
Section 17 Clock Pulse Generator
445
Overview
445
Block Diagram
446
Oscillator Circuit
446
Connecting a Crystal Resonator
448
External Clock Input
450
Duty Adjustment Circuit
450
Prescalers
450
Frequency Divider
451
Register Configuration
451
Division Control Register (DIVCR)
452
Usage Notes
453
Section 18 Power-Down State
453
Overview
455
Register Configuration
455
System Control Register (SYSCR)
457
Module Standby Control Register H (MSTCRH)
458
Module Standby Control Register L (MSTCRL)
460
Sleep Mode
460
Transition to Sleep Mode
460
Exit From Sleep Mode
460
Software Standby Mode
460
Transition to Software Standby Mode
461
Exit From Software Standby Mode
461
Selection of Waiting Time for Exit From Software Standby Mode
463
Sample Application of Software Standby Mode
463
Note
464
Hardware Standby Mode
464
Transition to Hardware Standby Mode
464
Exit From Hardware Standby Mode
464
Timing for Hardware Standby Mode
465
Module Standby Function
465
Module Standby Timing
465
Read/Write in Module Standby
465
Usage Notes
466
System Clock Output Disabling Function
467
Section 19 Electrical Characteristics - Preliminary
467
Absolute Maximum Ratings
468
DC Characteristics
478
AC Characteristics
484
A/D Conversion Characteristics
486
D/A Conversion Characteristics
487
Operational Timing
487
Clock Timing
488
Control Signal Timing
490
Bus Timing
494
TPC and I/O Port Timing
494
Timer Input/Output Timing
495
SCI Input/Output Timing
497
Appendix A Instruction Set
497
Instruction List
499
Data Transfer Instructions
501
Arithmetic Instructions
506
Bit Manipulation Instructions
512
Operation Code Maps
515
Number of States Required for Execution
524
Appendix B Internal I/O Registers
524
Address List
539
Functions
539
B.2 Functions
603
Appendix C I/O Port Block Diagrams
603
Port 4 Block Diagram
604
Port 6 Block Diagrams
608
Port 7 Block Diagrams
609
Port 8 Block Diagrams
613
Port 9 Block Diagrams
619
Port a Block Diagrams
622
Port B Block Diagrams
628
Appendix D Pin States
628
Port States in Each Mode
631
Pin States at Reset
633
Appendix E Timing of Transition to and Recovery From Hardware Standby Mode
634
Appendix F Product Code Lineup
635
Appendix G Package Dimensions
638
Appendix H Comparison of H8/300H Series Product Specifications
638
Differences Between H8/3067 and H8/3062 Series, H8/3048 Series, H8/3006 and H8/3007, and H8/3008
641
Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B)
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