ST STM32G0 1 Series Reference Manual page 587

RM0444
Bit 12 OIS3: Output Idle state 3 (OC3 output)
Refer to OIS1 bit
Bit 11 OIS2N: Output Idle state 2 (OC2N output)
Refer to OIS1N bit
Bit 10 OIS2: Output Idle state 2 (OC2 output)
Refer to OIS1 bit
Bit 9 OIS1N: Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
Bit 8 OIS1: Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
Bit 7 TI1S: TI1 selection
0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Bits 6:4 MMS[2:0]: Master mode selection
These bits allow selected information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is
010: Update - The update event is selected as trigger output (TRGO). For instance a master
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
100: Compare - OC1REFC signal is used as trigger output (TRGO)
101: Compare - OC2REFC signal is used as trigger output (TRGO)
110: Compare - OC3REFC signal is used as trigger output (TRGO)
111: Compare - OC4REFC signal is used as trigger output (TRGO)
Note: The clock of the slave timer or ADC must be enabled prior to receive events from the
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
(LOCK bits in TIMx_BDTR register).
(LOCK bits in TIMx_BDTR register).
reset is generated by the trigger input (slave mode controller configured in reset mode)
then the signal on TRGO is delayed compared to the actual reset.
useful to start several timers at the same time or to control a window in which a slave
timer is enable. The Counter Enable signal is generated by a logic AND between CEN
control bit and the trigger input when configured in gated mode. When the Counter
Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the
master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
timer can then be used as a prescaler for a slave timer.
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO).
master timer, and must not be changed on-the-fly while triggers are received from the
master timer.
RM0444 Rev 5
Advanced-control timer (TIM1)
587/1390
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