ST STM32G0 1 Series Reference Manual page 211

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Bits 19:18 LPTIM1SEL[1:0]: LPTIM1 clock source selection

Bits 17:16 Reserved, must be kept at reset value.

Bits 15:14 I2C2I2S1SEL[1:0]: I2C2/I2S1 clock source selection

Note: On the STM32G0B1xx and STM32G0C1xx, the bitfield selects the clock to the I2C2

Bits 13:12 I2C1SEL[1:0]: I2C1 clock source selection

Bits 11:10 LPUART1SEL[1:0]: LPUART1 clock source selection

Bits 9:8 LPUART2SEL[1:0]: LPUART2 clock source selection

Bit 7 Reserved, must be kept at reset value.

Bit 6 CECSEL: HDMI CEC clock source selection

This bitfield is controlled by software to select LPTIM1 clock source as follows:

This bitfield is controlled by software to select I2S1/I2C2 clock source as follows:

00: PCLK/SYSCLK

01: SYSCLK/PLLPCLK

10: HSI16/HSI16

11: Reserved/I2S_CKIN

peripheral. On the other devices, it selects the clock to the I2S1 peripheral.

This bitfield is controlled by software to select I2C1 clock source as follows:

11: Reserved

This bitfield is controlled by software to select LPUART1 clock source as follows:

This bitfield is controlled by software to select LPUART2 clock source as follows:

This bit is set and cleared by software. It selects the HDMI CEC clock source as follows:

0: HSI16 divided by 488

RM0444 Rev 5

Reset and clock control (RCC)

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