ST STM32G0 1 Series Reference Manual page 204

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Reset and clock control (RCC)

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved with zero reset value. Refer to

Section 1.4: Availability of

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 RNGSMEN: RNG clock enable during Sleep and Stop mode

Bits 17 Reserved, must be kept at reset value.

Bit 16 AESSMEN: AES hardware accelerator clock enable during Sleep mode

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 CRCSMEN: CRC clock enable during Sleep mode

Bits 11:10 Reserved, must be kept at reset value.

Bit 9 SRAMSMEN: SRAM clock enable during Sleep mode

Bit 8 FLASHSMEN: Flash memory interface clock enable during Sleep mode

peripherals.

Set and cleared by software.

Set and cleared by software.

Set and cleared by software.

Set and cleared by software.

Set and cleared by software.

This bit can be activated only when the Flash memory is in power down mode.

RM0444 Rev 5

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