ST STM32G0 1 Series Reference Manual page 181

RM0444
31 30 29
MCOPRE[3:0]
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15 14 13
Res. PPRE[2:0]
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1. Only significant on devices integrating the corresponding output, otherwise reserved. Refer to
peripherals.
Bits 31:28 MCOPRE[3:0]: Microcontroller clock output prescaler
Note: Values above 0111 are only significant for STM32G0B1xx and STM32G0C1xx.
Bits 27:24 MCOSEL[3:0]: Microcontroller clock output clock selector
Note: This clock output may have some truncated cycles at startup or during MCO clock
28 27 26 25
MCOSEL[3:0]
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12 11 10 9
HPRE[3:0]
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This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO
output as follows:
0000: 1
0001: 2
0010: 4
...
0111: 128
1000: 256
1001: 512
1010: 1024
Other: reserved
It is highly recommended to set this field before the MCO output is enabled.
Reserved for the other devices.
This bitfield is controlled by software. It sets the clock selector for MCO output as follows:
0000: no clock, MCO output disabled
0001: SYSCLK
0010: HSI48
0011: HSI16
0100: HSE
0101: PLLRCLK
0110: LSI
0111: LSE
1000: PLLPCLK
1001: PLLQCLK
1010: RTCCLK
1011: RTC WAKEUP
source switching.
Values above 0111 and the value 0010 are only significant for STM32G0B1xx and
STM32G0C1xx. Reserved for the other devices.
24 23 22
MCO2PRE[3:0]
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8 7 6
Res. Res.
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RM0444 Rev 5
Reset and clock control (RCC)
21 20 19 18
(1)
MCO2SEL[3:0]
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5 4 3 2
SWS[2:0]
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Section 1.4: Availability of
17 16
(1)
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1 0
SW[2:0]
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