Interrupts And Events; Nested Vectored Interrupt Controller (Nvic); Systick Calibration Value Register; Interrupt And Exception Vectors - ST STM32F102 Series Reference Manual

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8

Interrupts and events

Medium-density devices are STM32F101xx and STM32F103xx microcontrollers where
the Flash memory density ranges between 32 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
This Section applies to the whole STM32F10xxx family, unless otherwise specified.
8.1

Nested vectored interrupt controller (NVIC)

Features
●
60 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3)
●
16 programmable priority levels (4 bits of interrupt priority are used)
●
Low-latency exception and interrupt handling
●
Power management control
●
Implementation of System Control Registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming see Chap 5 Exceptions & Chap 8 Nested Vectored
Interrupt Controller of the ARM Cortex™-M3 Technical Reference Manual.
8.1.1

SysTick calibration value register

The SysTick calibration value is fixed to 9000 which allows the generation of a time base of
1ms with the SysTick clock set to 9 MHz (max HCLK/8).
8.1.2

Interrupt and exception vectors

Table 36.
-
-3
-2
-1
0
1
2
Vector table
Type of
Acronym
priority
- -
fixed Reset
fixed NMI
fixed HardFault
settable MemManage
settable BusFault
settable UsageFault
Description
Reserved
Reset
Non maskable interrupt. The RCC
Clock Security System (CSS) is
linked to the NMI vector.
All class of fault
Memory management
Pre-fetch fault, memory access fault
Undefined instruction or illegal state
Interrupts and events
Address
0x0000_0000
0x0000_0004
0x0000_0008
0x0000_000C
0x0000_0010
0x0000_0014
0x0000_0018
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