Interrupts And Events; Nested Vectored Interrupt Controller (Nvic); Systick Calibration Value Register; Interrupt And Exception Vectors - ST STM32F100 Series Reference Manual

Interrupts and events

8 Interrupts and events
Low-density value line devices are STM32F100xx microcontrollers where the flash
memory density ranges between 16 and 32 Kbytes.
Medium-density value line devices are STM32F100xx microcontrollers where the flash
memory density ranges between 64 and 128 Kbytes.
High-density value line devices are STM32F100xx microcontrollers where the flash
memory density ranges between 256 and 512 Kbytes.
This section applies to the whole STM32F100xx family, unless otherwise specified.
8.1

Nested vectored interrupt controller (NVIC)

Features
•
60 maskable interrupt channels in high-density value line devices and 56 in low and
medium-density value line devices (not including the sixteen Cortex
lines)
•
16 programmable priority levels (4 bits of interrupt priority are used)
•
Low-latency exception and interrupt handling
•
Power management control
• Implementation of System Control registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to STM32F100xx Cortex
manual (see
8.1.1

SysTick calibration value register

The SysTick calibration value is set to 9000, which gives a reference time base of 3 ms with
the SysTick clock set to 3 MHz (max HCLK/8).
8.1.2

Interrupt and exception vectors

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Related documents on page

Table 50. Vector table for STM32F100xx devices

Type of
Acronym
priority
- -
fixed Reset
1).
Description
Reserved
Reset
RM0041 Rev 6
RM0041
®
-M3 interrupt
®
-M3 programming
Address
0x0000_0000
0x0000_0004