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AN3320
Application note
Getting started with STM32F20xxx/21xxx MCU
hardware development
Introduction
This application note is intended for system designers who require a hardware
implementation overview of the development board features such as the power supply, the
clock management, the reset control, the boot mode settings and the debug management. It
shows how to use the high-density performance line STM32F20xxx/21xxx product families
and describes the minimum hardware resources required to develop an
STM32F20xxx/21xxx application.
Detailed reference design schematics are also contained in this document with descriptions
of the main components, interfaces and modes.
August 2011
Doc ID 18267 Rev 2
1/29
www.st.com
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Table of Contents
Related Manuals for ST STM32F20 Series
Summary of Contents for ST STM32F20 Series
- Page 1 STM32F20xxx/21xxx application. Detailed reference design schematics are also contained in this document with descriptions of the main components, interfaces and modes. August 2011 Doc ID 18267 Rev 2 1/29 www.st.com...
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Page 2: Table Of Contents
Contents AN3320 Contents Power supplies ..........6 Introduction . - Page 3 AN3320 Contents Recommendations ......... 21 Printed circuit board .
- Page 4 List of tables AN3320 List of tables Table 1. Boot modes............. 16 Table 2.
- Page 5 AN3320 List of figures List of figures Figure 1. Power supply overview ........... . . 6 Figure 2.
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Page 6: Power Supplies
Power supplies AN3320 Power supplies Introduction The device requires a 1.8 V to 3.6 V operating voltage supply (V ), excepted the WLCSP package witch requires 1.65 V to 3.6 V. An embedded regulator is used to supply the internal 1.2 V digital power. The real-time clock (RTC) and backup registers can be powered from the V voltage when the main V... -
Page 7: Independent A/D Converter Supply And Reference Voltage
AN3320 Power supplies 1.1.1 Independent A/D converter supply and reference voltage To improve conversion accuracy, the ADC has an independent power supply that can be filtered separately, and shielded from noise on the PCB. ● the ADC voltage supply input is available on a separate V ●... -
Page 8: Power Supply Schemes
Power supplies AN3320 Power supply schemes The circuit is powered by a stabilized power supply, V ● Caution: – The V voltage range is 1.8 V to 3.6 V (and 1.65 V to 3.6 V for WLCSP64+2 package) ● The V pins must be connected to V with external decoupling capacitors: one single Tantalum or Ceramic capacitor (min. -
Page 9: Reset & Power Supply Supervisor
AN3320 Power supplies Figure 2. Power supply scheme 1. Optional. If a separate, external reference voltage is connected on V , the two capacitors (100 nF and REF+ 1 µF) must be connected. 2. V + is either connected to V or to V 3. -
Page 10: Programmable Voltage Detector (Pvd)
Power supplies AN3320 Figure 3. Power-on reset/power-down reset waveform 1. t is approximately 2.6 ms. V rising edge is 1.74 V (typ.) and V falling edge is RSTTEMPO POR/PDR POR/PDR 1.70 V (typ.). Refer to STM32F20xxx/21xxx datasheets for actual value. 1.3.2 Programmable voltage detector (PVD) You can use the PVD to monitor the V... -
Page 11: System Reset
AN3320 Power supplies 1.3.3 System reset A system reset sets all registers to their reset values except for the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure A system reset is generated when one of the following events occurs: A low level on the NRST pin (external reset) window watchdog end-of-count condition (WWDG reset) Independent watchdog end-of-count condition (IWDG reset) -
Page 12: Clocks
Clocks AN3320 Clocks Three different clock sources can be used to drive the system clock (SYSCLK): ● HSI oscillator clock (high-speed internal clock signal) ● HSE oscillator clock (high-speed external clock signal) ● PLL clock The devices have two secondary clock sources: ●... -
Page 13: External Source (Hse Bypass)
AN3320 Clocks 2.1.1 External source (HSE bypass) In this mode, an external clock source must be provided. It can have a frequency from 1 to 16 MHz (refer to STM32F20xxx/21xxx datasheets for actual max value). The external clock signal (square, sine or triangle) with a duty cycle of about 50%, has to drive the OSC_IN pin while the OSC_OUT pin must be left in the high impedance state (see Figure 7 Figure... -
Page 14: Lse Osc Clock
A 0 Ω resistor would work but would not be The value of R optimal. To fine tube R value, refer to AN2867 - Oscillator design guide for ST microcontrollers. 2.2.1 External source (LSE bypass) In this mode, an external clock source must be provided. -
Page 15: Clock Security System (Css)
HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too. For details, see the STM32F20xxx/21xxx (RM0033) reference manuals available from the STMicroelectronics website www.st.com. Doc ID 18267 Rev 2 15/29... -
Page 16: Boot Configuration
Boot configuration AN3320 Boot configuration Boot mode selection In the STM32F20xxx/21xxx, three different boot modes can be selected by means of the BOOT[1:0] pins as shown in Table Table 1. Boot modes BOOT mode selection pins Boot mode Aliasing BOOT1 BOOT0 Main Flash memory is selected as boot Main Flash memory... -
Page 17: Embedded Boot Loader Mode
USB OTG FS, however, can only function if an external clock (HSE) multiple of 1 MHz (between 4 and 26 MHz)is present. This embedded boot loader is located in the System memory and is programmed by ST during production. For additional information, refer to AN2606. -
Page 18: Debug Management
Debug management AN3320 Debug management Introduction The Host/Target interface is the hardware equipment that connects the host to the application board. This interface is made of three components: a hardware debug tool, a JTAG or SW connector and a cable connecting the host to the debug tool. Figure 11 shows the connection of the host to the evaluation board STM3220G-EVAL. -
Page 19: Flexible Swj-Dp Pin Assignment
Table 3 shows the different possibilities to release some pins. For more details, see the STM32F20xxx/21xxx (RM0033) reference manual, available from the STMicroelectronics website www.st.com. 4.3.3 Internal pull-up and pull-down resistors on JTAG pins The JTAG input pins must not be floating since they are directly connected to flip-flops to control the debug mode features. -
Page 20: Swj Debug Port Connection With Standard Jtag Connector
Debug management AN3320 To avoid any uncontrolled I/O levels, the STM32F20xxx/21xxx embeds internal pull-up and pull-down resistors on JTAG input pins: ● JNTRST: Internal pull-up ● JTDI: Internal pull-up ● JTMS/SWDIO: Internal pull-up ● TCK/SWCLK: Internal pull-down Once a JTAG I/O is released by the user software, the GPIO controller takes control again. The reset states of the GPIO control registers put the I/Os in the equivalent state: ●... -
Page 21: Recommendations
AN3320 Recommendations Recommendations Printed circuit board For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a separate layer dedicated to ground (V ) and another dedicated to the V supply. This provides good decoupling and a good shielding effect. For many applications, economical reasons prohibit the use of this type of board. -
Page 22: Other Signals
Recommendations AN3320 Figure 13. Typical layout for V pair Via to V Via to V Cap. STM32F20xxx/21xxx Other signals When designing an application, the EMC performance can be improved by closely studying: ● Signals for which a temporary disturbance affects the running process permanently (the case of interrupts and handshaking strobe signals, and not the case for LED commands). -
Page 23: Reference Design
AN3320 Reference design Reference design Description The reference design shown in Figure 14, is based on the STM32F207IF(H6), a highly ™ integrated microcontroller running at 120 MHz, that combines the Cortex -M3 32-bit RISC CPU core with 1 Mbyte of embedded Flash memory and up to 128 + 4 Kbytes of high-speed SRAM This reference design can be tailored to any other STM32F20xxx/21xxx device with different package, using the pins correspondence given in... -
Page 24: Component References
Reference design AN3320 Component references Table 4. Mandatory components Id Components name Reference Quantity Comments 1 Microcontroller STM32F207IG(H6) 176-pin package Ceramic capacitors (decoupling 2 Capacitors 100 nF capacitors) 3 Capacitor 10 µF Ceramic capacitor (decoupling capacitor) Table 5. Optional components Id Components name Reference Quantity... -
Page 25: Figure 14. Stm32F207Ig(H6) Microcontroller Reference Schematic
AN3320 Reference design Figure 14. STM32F207IG(H6) microcontroller reference schematic 1. If no external battery is used in the application, it is recommended to connect V externally to V 2. To be able to reset the device from the tools this resistor has to be kept. Doc ID 18267 Rev 2 25/29... -
Page 26: Table 6. Reference Connection For All Packages
Reference design AN3320 Table 6. Reference connection for all packages numbers Pin numbers for Pin numbers for LQFP packages for BGA WLCSP package Pin name package 176 pins 144 pins 100 pins 64 pins 176 pins 64+2 pins OSC_IN OSC_OUT PC15- OSC32_OUT PC14-... - Page 27 AN3320 Reference design Table 6. Reference connection for all packages (continued) numbers Pin numbers for Pin numbers for LQFP packages for BGA WLCSP package Pin name package 176 pins 144 pins 100 pins 64 pins 176 pins 64+2 pins DD_4 DD_5 DD_6 DD_7...
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Page 28: Revision History
Revision history AN3320 Revision history Table 7. Document revision history Date Revision Changes 25-Feb-2011 Initial release. Updated REGOFF and IRROFF pin configuration. Updated standby mode in Chapter 1.1.3: Voltage regulator. Updated voltage regulator configuration in Chapter 1.2: Power 22-Aug-2011 supply schemes. - Page 29 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
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