ST STM32G0 1 Series Reference Manual page 78

Embedded Flash memory (FLASH)
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PGSERR: Programming Sequence Error
PGSERR is set if one of the following conditions occurs:
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WRPERR: Write Protection Error
WRPERR is set if one of the following conditions occurs:
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MISSERR: Fast Programming Data Miss Error
In fast programming: all the data must be written successively. MISSERR is set if the
previous data programmation is finished and the next data to program is not written yet.
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FASTERR: Fast Programming Error
In fast programming: FASTERR is set if one of the following conditions occurs:
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If an error occurs during a program or erase operation, one of the following error flags of the
FLASH status register (FLASH_SR)
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PROGERR, SIZERR, PGAERR, PGSERR, MISSERR (program error flags)
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WRPERR (protection error flag)
In this case, if the error interrupt enable bit ERRIE of the
(FLASH_CR)
FLASH status register (FLASH_SR)
Note: If several successive errors are detected (for example, in case of DMA transfer to the Flash
memory), the error flags cannot be cleared until the end of the successive write request.
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In fast programming: the data to program doesn't belong to the same row than the
previous programmed double words, or the address to program is not greater than
the previous one.
In the standard programming sequence or the fast programming sequence: a data
is written when PG and FSTPG are cleared.
In the standard programming sequence or the fast programming sequence: MER1
and PER are not cleared when PG or FSTPG is set.
In the fast programming sequence: the Mass erase is not performed before setting
the FSTPG bit.
In the mass erase sequence: PG, FSTPG, and PER are not cleared when MER1 is
set.
In the page erase sequence: PG, FSTPG and MER1 are not cleared when PER is
set.
PGSERR is set also if PROGERR, SIZERR, PGAERR, WRPERR, MISSERR,
FASTERR or PGSERR is set due to a previous programming error.
Attempt to program or erase in a write protected area (WRP) or in a PCROP area.
Attempt to perform a mass erase when one page or more is protected by WRP or
PCROP.
The debug features are connected or the boot is executed from SRAM or from
system Flash memory when the read protection (RDP) is set to Level 1.
Attempt to modify the option bytes when the read protection (RDP) is set to
Level 2.
when FSTPG bit is set for more than 8 ms, which generates a time-out detection
when the row fast programming has been interrupted by a MISSERR, PGAERR,
WRPERR or SIZERR
is set, an interrupt is generated and the operation error flag OPERR of the
is set:
is set.
RM0444 Rev 5
FLASH control register
RM0444