ST STM32G0 1 Series Reference Manual page 136

Power control (PWR)
Entering Stop 0 mode
The MCU enters Stop 0 mode according to section
SLEEPDEEP bit in the Cortex
Refer to
If Flash memory programming is ongoing, the Stop 0 mode entry is delayed until the
memory access is finished.
If an access to the APB domain is ongoing, The Stop 0 mode entry is delayed until the APB
access is finished.
In Stop 0 mode, the following features can be selected by programming individual control
bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started, it cannot be stopped except upon a reset. See
Section 28.3: IWDG functional
•
real-time clock (RTC): this is configured by the RTCEN bit in the
register
• Internal RC oscillator (LSI): this is configured by the LSION bit in the
register
•
External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the
domain control register
Several peripherals can be used in Stop 0 mode and can add consumption if they are
enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LPTIM1,
LPTIM2, USART1, USART2, LPUART, and I2C1.
The DAC, the comparators, and the PVD can be used in Stop 0 mode.
The ADC, the VREFBUF buffer, and the temperature sensor can consume power during the
Stop 0 mode, unless they are disabled before entering this mode.
Exiting Stop 0 mode
The MCU exits Stop 0 mode according to section
Refer to
When exiting Stop 0 mode by issuing an interrupt or a wakeup event, the HSISYS oscillator
is selected as system clock. If the device is configured to wake up in Low-power run mode,
the HSIDIV bits in RCC_CR register must be configured prior to entering Stop 0 mode to
provide a frequency not greater than 2 MHz.
When exiting Stop 0 mode, the MCU is either in Run mode (Range 1 or Range 2 depending
on VOS bit in PWR_CR1) or in Low-power run mode if the bit LPR is set in the
control register 1
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Table 30: Stop 0 mode summary
(RCC_BDCR).
(RCC_CSR).
(RCC_BDCR).
Table 30: Stop 0 mode summary
(PWR_CR1).
Entering low-power
-M0+ System Control register is set.
for details on how to enter Stop 0 mode.
description.
Entering low-power
for details on how to exit Stop 0 mode.
RM0444 Rev 5
RM0444
modes, when the
RTC domain control
Control/status
RTC
modes.
Power