Interrupts And Events; Nested Vectored Interrupt Controller (Nvic); Nvic Features; Systick Calibration Value Register - ST STM32F423 Reference Manual

RM0430
10

Interrupts and events

10.1

Nested vectored interrupt controller (NVIC)

10.1.1

NVIC features

The nested vector interrupt controller NVIC includes the following features:
•
52 maskable interrupt channels (not including the 16 interrupt lines of Cortex
FPU)
•
16 programmable priority levels (4 bits of interrupt priority are used)
•
low-latency exception and interrupt handling
•
power management control
•
implementation of system control registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to programming manual PM0214.
10.1.2

SysTick calibration value register

The SysTick calibration value is fixed to 10500, which gives a reference time base of 1 ms
with the SysTick clock set to 10.5 MHz (HCLK/8, with HCLK set to 84 MHz).
10.1.3

Interrupt and exception vectors

See Table
10.2

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of up to 23 edge detectors for generating
event/interrupt requests. Each input line can be independently configured to select the type
(interrupt or event) and the corresponding trigger event (rising or falling or both). Each line
can also masked independently. A pending register maintains the status line of the interrupt
requests.
40, for the vector table for the STM32F413/423 devices.
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Interrupts and events
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