ST STM32G0 1 Series Reference Manual page 192

Reset and clock control (RCC)
31 30 29 28
DAC1
LPTIM1 LPTIM2 PWR
(1)
RST RST RST
RST
rw rw rw rw
15 14 13 12
FDCA
SPI3 USB
SPI2
N
(1) (1)
RST
RST RST
RST
rw rw rw rw
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to
of peripherals.
Bit 31 LPTIM1RST: Low Power Timer 1 reset
Bit 30 LPTIM2RST: Low Power Timer 2 reset
Bit 29 DAC1RST: DAC1 interface reset
Bit 28 PWRRST: Power interface reset
Bit 27 DBGRST: Debug support reset
Bit 26 UCPD2RST: UCPD2 reset
Bit 25 UCPD1RST: UCPD1 reset
Bit 24 CECRST: HDMI CEC reset
192/1390
27 26 25
UCPD
UCPD1
DBG
2
(1)
RST
RST
(1)
RST
rw rw rw
11 10 9
USART6
(1)
Res. Res.
(1)
RST
rw
Set and cleared by software.
0: No effect
1: Reset LPTIM1
Set and cleared by software.
0: No effect
1: Reset LPTIM2
Set and cleared by software.
0: No effect
1: Reset DAC1 interface
Set and cleared by software.
0: No effect
1: Reset PWR
Set and cleared by software.
0: No effect
1: Reset DBG
Set and cleared by software.
0: No effect
1: Reset UCPD2
Set and cleared by software.
0: No effect
1: Reset UCPD1
Set and cleared by software.
0: No effect
1: Reset the HDMI CEC
24 23 22
CEC I2C3
I2C2
(1) (1)
RST
RST RST
rw rw rw
8 7 6
LP
USART5 UART2
Res.
(1) (1)
RST
RST
rw rw
(1)
(1)
(1)
(1)
RM0444 Rev 5
21 20 19
LP
USART4 USART3
I2C1
UART1
(1)
RST
RST RST
RST
rw rw rw
5 4 3
TIM7 TIM6 TIM4
Res.
(1) (1)
RST RST RST
rw rw
Section 1.4: Availability
RM0444
18 17 16
CRSR
USART2
(1) (1)
RST
ST
rw rw rw
2 1 0
TIM3 TIM2
(1)
RST RST
rw rw rw