ST STM32G0 1 Series Reference Manual page 200

Reset and clock control (RCC)
Bit 17 USART2EN: USART2 clock enable
Bit 16 CRSEN: CRS clock enable
Bit 15 SPI3EN: SPI3 clock enable
Bit 14 SPI2EN: SPI2 clock enable
Bit 13 USBEN: USB clock enable
Bit 12 FDCANEN: FDCAN clock enable
Bit 11 WWDGEN: WWDG clock enable
Bit 10 RTCAPBEN: RTC APB clock enable
Bit 9 USART6EN: USART6 clock enable
Bit 8 USART5EN: USART5 clock enable
Bit 7 LPUART2EN: LPUART2 clock enable
200/1390
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
to enable the window watchdog clock. Cleared by hardware system
Set by software
reset
0: Disable
1: Enable
This bit can also be set by hardware if the WWDG_SW option bit is 0.
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
(1)
(1)
(1)
(1)
(1)
(1)
(1)
RM0444 Rev 5
RM0444