ST STM32G0 1 Series Reference Manual page 800

General-purpose timers (TIM15/TIM16/TIM17)
Bit 13 BKP: Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 12 BKE: Break enable
0: Break inputs (BRK and CCS clock failure event) disabled
1; Break inputs (BRK and CCS clock failure event) enabled
This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 11 OSSR: Off-state selection for Run mode
This bit is used when MOE=1 on channels that have a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented
in the timer.
See OC/OCN enable description for more details
enable register (TIM15_CCER) on page
0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
Bit 10 OSSI: Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details
enable register (TIM15_CCER) on page
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
Bits 9:8 LOCK[1:0]: Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
800/1390
in TIMx_BDTR register).
Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
is taken over by the AFIO logic, which forces a Hi-Z state)
or CCxNE=1 (the output is still controlled by the timer).
bits in TIMx_BDTR register).
CCxNE=1. OC/OCN enable output signal=1)
bits in TIMx_BDTR register).
register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
register, as long as the related channel is configured in output through the CCxS bits) as
well as OSSR and OSSI bits can no longer be written.
TIMx_CCMRx registers, as long as the related channel is configured in output through
the CCxS bits) can no longer be written.
has been written, their content is frozen until the next reset.
(Section 25.5.9: TIM15 capture/compare
793).
(Section 25.5.9: TIM15 capture/compare
793).
RM0444 Rev 5
RM0444