Nested Vectored Interrupt Controller (Nvic); Accessing The Cortex-M0 Nvic Registers Using Cmsis; Table 25. Nvic Register Summary; Table 26. Cmsis Access Nvic Functions - ST STM32F0 Series Programming Manual

Core peripherals
4.2

Nested vectored interrupt controller (NVIC)

This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it
uses. The NVIC supports:
● Up to 32 interrupts
●
A programmable priority level of 0-192 in steps of 64 for each interrupt. A higher level
corresponds to a lower priority, so level 0 is the highest interrupt priority
● Level and pulse detection of interrupt signals
●
Interrupt tail-chaining
● An external Non-maskable interrupt (NMI)
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
The hardware implementation of the NVIC registers is:
Table 25. NVIC register summary
Address Name
0xE000E100 ISER
0XE000E180 ICER
0XE000E200 ISPR
0XE000E280 ICPR
0xE000E400-
IPR0-IPR7
0xE000E41C
4.2.1

Accessing the Cortex-M0 NVIC registers using CMSIS

CMSIS functions enable software portability between different Cortex-M profile processors.
To access the NVIC registers when using CMSIS, use the following functions:
Table 26. CMSIS access NVIC functions
CMSIS function
void NVIC_EnableIRQ(IRQn_Type IRQn)
void NVIC_DisableIRQ(IRQn_Type IRQn)
void NVIC_SetPendingIRQ(IRQn_Type IRQn)
void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1. The input parameter IRQn is the IRQ number,
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Type Reset value
RW 0x00000000 Table 4.2.2: Interrupt set-enable register (ISER) on page 71
RW 0x00000000 Table 4.2.3: Interrupt clear-enable register (ICER) on page 71
RW 0x00000000 Table 4.2.4: Interrupt set-pending register (ISPR) on page 72
Table 4.2.5: Interrupt clear-pending register (ICPR) on
RW 0x00000000
page 72
RW 0x00000000 Table 4.2.6: Interrupt priority register (IPR0-IPR7) on page 73
(1)
Doc ID 022979 Rev 1
Description
Description
Enables an interrupt or exception.
Disables an interrupt or exception.
Sets pending status of interrupt or exception to 1.
Clears pending status of interrupt / exception to 0.
Reads the pending status of interrupt / exception.
Returns non-zero value if pending status is set to 1.
Sets priority of an interrupt / exception with configurable
priority level to 1.
Reads priority of an interrupt or exception with
configurable priority level.
Returns the current priority level.
PM0215