ST STM32G0 1 Series Reference Manual page 331

RM0444
Reset value: 0x0000 0000
EXTIm fields contain only the number of bits in line with the nb_ioport configuration.
31 30 29
EXTIm+3[7:0]
rw rw rw
15 14 13
EXTIm+1[7:0]
rw rw rw
Bits 31:24 EXTIm+3[7:0]: EXTIm+3 GPIO port selection (m = 4 * (x - 1))
These bits are written by software to select the source input for EXTIm+3 external interrupt.
0x00: PA[m+3] pin
0x01: PB[m+3] pin
0x02: PC[m+3] pin
0x03: PD[m+3] pin
0x04: reserved
0x05: PF[m+3] pin
Others reserved
Bits 23:16 EXTIm+2[7:0]: EXTIm+2 GPIO port selection (m = 4 * (x - 1))
These bits are written by software to select the source input for EXTIm+2 external interrupt.
0x00: PA[m+2] pin
0x01: PB[m+2] pin
0x02: PC[m+2] pin
0x03: PD[m+2] pin
0x04: reserved
0x05: PF[m+2] pin
Others reserved
Bits 15:8 EXTIm+1[7:0]: EXTIm+1 GPIO port selection (m = 4 * (x - 1))
These bits are written by software to select the source input for EXTIm+1 external interrupt.
0x00: PA[m+1] pin
0x01: PB[m+1] pin
0x02: PC[m+1] pin
0x03: PD[m+1] pin
0x04: reserved
0x05: PF[m+1] pin
Others reserved
Bits 7:0 EXTIm[7:0]: EXTIm GPIO port selection (m = 4 * (x - 1))
These bits are written by software to select the source input for EXTIm external interrupt.
0x00: PA[m] pin
0x01: PB[m] pin
0x02: PC[m] pin
0x03: PD[m] pin
0x04: reserved
0x05: PF[m] pin
Others reserved
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
Extended interrupt and event controller (EXTI)
24 23 22
rw rw rw
8 7 6
rw rw rw
RM0444 Rev 5
21 20 19 18
EXTIm+2[7:0]
rw rw rw rw
5 4 3 2
EXTIm[7:0]
rw rw rw rw
17 16
rw rw
1 0
rw rw
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