ST STM32G0 1 Series Reference Manual page 210

Reset and clock control (RCC)
31 30 29
ADCSEL[1:0]
RNGDIV[1:0]
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15 14 13
I2C2I2S1SEL[1:0] I2C1SEL[1:0]
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1. Only significant on devices integrating the corresponding peripheral supporting independent clock selection (or supporting
the corresponding function), otherwise reserved. Refer to
implementation.
Bits 31:30 ADCSEL[1:0]: ADCs clock source selection
Bits 29:28 RNGDIV[1:0]: Division factor of RNG clock divider
Bits 27:26 RNGSEL[1:0]: RNG clock source selection
Bit 25 Reserved, must be kept at reset value.
Bit 24 TIM15SEL: TIM15 clock source selection
Bit 23 Reserved, must be kept at reset value.
Bit 22 TIM1SEL: TIM1 clock source selection
Bits 21:20 LPTIM2SEL[1:0]: LPTIM2 clock source selection
210/1390
28 27 26 25
(1) (1)
Res.
RNGSEL[1:0]
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12 11 10 9
LPUART2SEL
LPUART1SEL
[1:0]
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This bitfield is controlled by software to select the clock source for ADC:
00: System clock
01: PLLPCLK
10: HSI16
11: Reserved
This bitfield is controlled by software to select the division factor as follows:
00: 1
01: 2
10: 4
11: 8
This bitfield is controlled by software to select the RNG clock as follows:
00: No clock
01: HSI16
10: SYSCLK
11: PLLQCLK
This bit is set and cleared by software. It selects TIM15 clock source as follows:
0: TIMPCLK
1: PLLQCLK
This bit is set and cleared by software. It selects TIM1 clock source as follows:
0: TIMPCLK
(1)
1: PLLQCLK
This bitfield is controlled by software to select LPTIM2 clock source as follows:
00: PCLK
01: LSI
10: HSI16
11: LSE
24 23 22
TIM15
TIM1
Res.
(1)
SEL
SEL
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8 7 6
CEC
Res.
(1)
SEL
[1:0]
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Section 1.4: Availability of peripherals
(1)
RM0444 Rev 5
21 20 19 18
LPTIM2SEL[1:0] LPTIM1SEL[1:0]
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5 4 3
USART3SEL USART2SEL
(1) (1)
[1:0] [1:0]
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and Section 33.4: USART
RM0444
17 16
Res. Res.
2 1 0
USART1SEL
[1:0]
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