ST STM32G0 1 Series Reference Manual page 188

Reset and clock control (RCC)
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 LSECSSF: LSE clock security system interrupt flag
Bit 8 CSSF: HSE clock security system interrupt flag
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYF: PLL ready interrupt flag
Bit 4 HSERDYF: HSE ready interrupt flag
Bit 3 HSIRDYF: HSI16 ready interrupt flag
Bit 2 HSI48RDYF: HSI48 ready interrupt flag
Bit 1 LSERDYF: LSE ready interrupt flag
Bit 0 LSIRDYF: LSI ready interrupt flag
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Set by hardware when a failure is detected in the LSE oscillator.
Cleared by software by setting the LSECSSC bit.
0: No clock security interrupt caused by LSE clock failure
1: Clock security interrupt caused by LSE clock failure
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Set by hardware when the PLL locks and PLLRDYIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Set by hardware when the HSE clock becomes stable and HSERDYIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response
to setting the HSION (refer to
but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not
set and no interrupt is generated.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI16 oscillator
1: Clock ready interrupt caused by the HSI16 oscillator
Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a
response to setting the HSI48ON (refer to
HSI48ON is not set but the HSI48 oscillator is enabled by the peripheral through a clock
request, this bit is not set and no interrupt is generated.
Cleared by software setting the HSI48RDYC bit.
0: No clock ready interrupt caused by the HSI48 oscillator
1: Clock ready interrupt caused by the HSI48 oscillator
Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
Clock control register (RCC_CR)
Clock control register (RCC_CR)
RM0444 Rev 5
RM0444
). When HSION is not set
). When