ST STM32G0 1 Series Reference Manual page 216

Reset and clock control (RCC)
Bit 31 LPWRRSTF: Low-power reset flag
Bit 30 WWDGRSTF: Window watchdog reset flag
Bit 29 IWDGRSTF: Independent window watchdog reset flag
Bit 28 SFTRSTF: Software reset flag
Bit 27 PWRRSTF: BOR or POR/PDR flag
Bit 26 PINRSTF: Pin reset flag
Bit 25 OBLRSTF: Option byte loader reset flag
Bit 24 Reserved, must be kept at reset value.
Bit 23 RMVF: Remove reset flags
216/1390
Set by hardware when a reset occurs due to illegal Stop, Standby, or Shutdown mode entry.
Cleared by setting the RMVF bit.
0: No illegal mode reset occurred
1: Illegal mode reset occurred
This operates only if nRST_STOP, nRST_STDBY or nRST_SHDW option bits are cleared.
Set by hardware when a window watchdog reset occurs.
Cleared by setting the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Set by hardware when an independent watchdog reset domain occurs.
Cleared by setting the RMVF bit.
0: No independent watchdog reset occurred
1: Independent watchdog reset occurred
Set by hardware when a software reset occurs.
Cleared by setting the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Set by hardware when a BOR or POR/PDR occurs.
Cleared by setting the RMVF bit.
0: No BOR or POR occurred
1: BOR or POR occurred
Set by hardware when a reset from the NRST pin occurs.
Cleared by setting the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Set by hardware when a reset from the Option byte loading occurs.
Cleared by setting the RMVF bit.
0: No reset from Option byte loading occurred
1: Reset from Option byte loading occurred
Set by software to clear the reset flags.
0: No effect
1: Clear reset flags
RM0444 Rev 5
RM0444