ST STM32G0 1 Series Reference Manual page 109

RM0444
Bit 20 nSWAP_BANK: Empty check boot configuration
Bit 19 WWDG_SW: Window watchdog selection
Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode
Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode
Bit 16 IDWG_SW: Independent watchdog selection
Bit 15 nRSTS_SHDW
Bit 14 nRST_STDBY
Bit 13 nRST_STOP
Bits 12:11 BORF_LEV[1:0]: BOR threshold at falling V
Bits 10:9 BORR_LEV[1:0]: BOR threshold at rising V
Bit 8 BOR_EN: Brown out reset enable
Bits 7:0 RDP[7:0]: Read protection level
Note: 0xAA: Level 0, read protection not active
This bit selects the bank that is the subject of empty check upon boot.
0: Bank 1
1: Bank 2
The bit is ignored when the BOOT_LOCK bit is set.
0: Hardware window watchdog
1: Software window watchdog
0: Independent watchdog counter is frozen in Standby mode
1: Independent watchdog counter is running in Standby mode
0: Independent watchdog counter is frozen in Stop mode
1: Independent watchdog counter is running in Stop mode
0: Hardware independent watchdog
1: Software independent watchdog
0: Reset generated when entering the Shutdown mode
1: No reset generated when entering the Shutdown mode
0: Reset generated when entering the Standby mode
1: No reset generated when entering the Standby mode
0: Reset generated when entering the Stop mode
1: No reset generated when entering the Stop mode
Falling V crossings this threshold activates the reset signal.
DD
00: BOR falling level 1 with threshold around 2.0 V
01: BOR falling level 2 with threshold around 2.2 V
10: BOR falling level 3 with threshold around 2.5 V
11: BOR falling level 4 with threshold around 2.8 V
Rising V crossings this threshold releases the reset signal.
DD
00: BOR rising level 1 with threshold around 2.1 V
01: BOR rising level 2 with threshold around 2.3 V
10: BOR rising level 3 with threshold around 2.6 V
11: BOR rising level 4 with threshold around 2.9 V
0: Configurable brown out reset disabled, power-on reset defined by POR/PDR levels
1: Configurable brown out reset enabled, values of BORR_LEV_RISING and
BORF_LEV_FALLING taken into account
0xCC: Level 2, chip read protection active
Others: Level 1, memories read protection active
supply
DD
supply
DD
RM0444 Rev 5
Embedded Flash memory (FLASH)
109/1390
118