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Embedded Flash memory (FLASH)
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:9 Reserved, must be kept at reset value.
Bits 8:0 PCROP1B_END[8:0]: PCROP1B area end offset (Bank 1)
Note: Values corresponding to addresses outside the Main memory are not allowed.
PCROP2A start address option bytes
Flash memory address: 0x1FFF 7838
Reset value: 0xFFFF FFFF (ST production value)
The register pertains to dual-bank devices only. In single-bank devices, it is reserved.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:9 Reserved, must be kept at reset value.
Bits 8:0 PCROP2A_STRT[8:0]: PCROP2A area start offset, Bank 2
Note: Values corresponding to addresses outside the Main memory are not allowed.
PCROP2A end address option bytes
Flash memory address: 0x1FFF 7840
Reset value: 0x0000 0000 (ST production value)
The register pertains to dual-bank devices only. In single-bank devices, it is reserved.
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
86/1390
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
PCROP1B_END contains the offset of the last PCROP subpage of the PCROP1B area (in
Bank 1 for dual-bank devices).
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
PCROP2A_STRT contains the offset of the first PCROP subpage of the PCROP2A area in
Bank 2 of dual-bank devices.
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
r
r
r
24
23
22
Res.
Res.
Res.
Res.
8
7
6
r
r
r
24
23
22
Res.
Res.
Res.
8
7
6
r
r
r
RM0444 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
PCROP1B_END[8:0]
r
r
r
r
21
20
19
18
Res.
Res.
Res.
5
4
3
2
PCROP2A_STRT[8:0]
r
r
r
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
PCROP2A_END[8:0]
r
r
r
r
RM0444
17
16
Res.
Res.
1
0
r
r
17
16
Res.
Res.
1
0
r
r
17
16
Res.
Res.
1
0
r
r
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- Memory Organization
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