ST STM32G0 1 Series Reference Manual page 296

Direct memory access controller (DMA)
Offset Register
DMA_CCR3
0x030
Reset value
DMA_CNDTR3
0x034
Reset value
DMA_CPAR3
0x038
Reset value
DMA_CMAR3
0x03C
Reset value
0x040 Reserved
DMA_CCR4
0x044
Reset value
DMA_CNDTR4
0x048
Reset value
DMA_CPAR4
0x04C
Reset value
DMA_CMAR4
0x050
Reset value
0x054 Reserved
DMA_CCR5
0x058
Reset value
DMA_CNDTR5
0x05C
Reset value
DMA_CPAR5
0x060
Reset value
DMA_CMAR5
0x064
Reset value
0x068 Reserved
DMA_CCR6
0x06C
Reset value
DMA_CNDTR6
0x070
Reset value
DMA_CPAR6
0x074
Reset value
DMA_CMAR6
0x078
Reset value
0x07C Reserved
DMA_CCR7
0x080
Reset value
296/1390
Table 50. DMA register map and reset values (continued)
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0
PA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
Reserved.
0
PA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
Reserved.
0
PA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
Reserved.
0
PA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
Reserved.
RM0444 Rev 5
0 0 0 0 0 0 0 0 0
NDTR[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
NDTR[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
NDTR[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
NDTR[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
RM0444
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0