Motorola PowerQUICC II MPC8280 Series Reference Manual page 32

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Number
28.5.7 SMC GCI C/I Channel RxBD ..................................................................... 28-36
28.5.8 SMC GCI C/I Channel TxBD...................................................................... 28-37
28.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM)...................... 28-37
29.1 MCC Operation Overview................................................................................. 29-2
29.1.1 MCC Data Structure Organization................................................................. 29-2
29.2 Global MCC Parameters .................................................................................... 29-4
29.3 Channel-Specific Parameters ............................................................................. 29-6
29.3.1 Channel-Specific HDLC Parameters ............................................................. 29-6
29.3.1.1 Internal Transmitter State (TSTATE)—HDLC Mode ............................... 29-7
29.3.1.2 Interrupt Mask (INTMSK)—HDLC Mode ............................................... 29-8
29.3.1.3 Channel Mode Register (CHAMR)—HDLC Mode.................................. 29-9
29.3.1.4 Internal Receiver State (RSTATE)—HDLC Mode ................................. 29-10
29.3.2 Channel-Specific Transparent Parameters................................................... 29-11
29.3.2.1 Internal Transmitter State (TSTATE)—Transparent Mode ..................... 29-13
29.3.2.2 Interrupt Mask (INTMSK)—Transparent Mode ..................................... 29-13
29.3.2.3 Channel Mode Register (CHAMR)—Transparent Mode........................ 29-13
29.3.2.4 Internal Receiver State (RSTATE)—Transparent Mode ......................... 29-15
29.3.3 MCC Parameters for AAL1 CES Usage...................................................... 29-15
29.3.3.1 Channel-Specific Parameters—AAL1 CES ............................................ 29-15
29.3.3.1.1 Interrupt Circular Table Entry and Interrupt Mask
29.3.3.2 Channel Mode Register (CHAMR)—AAL1 CES .................................. 29-16
29.3.4 Channel-Specific SS7 Parameters ............................................................... 29-18
29.3.4.1 Extended Channel Mode Register (ECHAMR)—SS7 Mode.................. 29-22
29.3.4.2 Signal Unit Error Monitor (SUERM)—SS7 Mode ................................. 29-24
29.3.4.2.1 SUERM in Japanese SS7..................................................................... 29-24
29.3.4.3 SS7 Configuration Register—SS7 Mode ................................................ 29-25
29.3.4.3.1 AERM Implementation ....................................................................... 29-26
29.3.4.3.2 AERM in Japanese SS7....................................................................... 29-26
29.3.4.3.3 Disabling SUERM ............................................................................... 29-26
29.3.4.4 SU Filtering—SS7 Mode......................................................................... 29-27
29.3.4.4.1 Comparison Mask................................................................................ 29-27
29.3.4.4.2 Comparison State Machine.................................................................. 29-27
29.3.4.4.3 Filtering Limitations ............................................................................ 29-28
29.3.4.4.4 Resetting the SU Filtering Mechanism................................................ 29-29
29.3.4.5 Octet Counting Mode—SS7 Mode.......................................................... 29-29
29.4 Channel Extra Parameters................................................................................ 29-29
29.5 Superchannels .................................................................................................. 29-30
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Freescale Semiconductor, Inc.
Contents
Title
Chapter 29
Multi-Channel Controllers (MCCs)
(INTMSK)—AAL1 CES................................................................. 29-16
MPC8280 PowerQUICC II Family Reference Manual
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