Register Description - Fujitsu MB91260B Series Hardware Manual

15.2

Register Description

This section explains the register configuration and function of using the multiplication
and addition calculator.
■ DSP-CSR (Control/Status Registers)
The control/status register is an 8-bit register. It consists of flags to change the multiplication and addition
macro state, control interrupts to the CPU, and indicate the status of the multiplication and addition macro.
This register is also used to set the conditions for conditional branching commands in the multiplication
and addition macro.
The 8-bit register always allows external R/W.
●
Control function
• Multiplication and addition macro state (calculation start/end) transition (GoDSP and HltDSP)
• Interrupt mask for CPU (IeDSP)
• Sets conditions for conditional branching command of multiplication and addition macro (USR2, USR1,
and USR0).
• Multiplication and addition macro state (calculation start/end) transition (GoDSP and HltDSP)
• Interrupt mask for CPU (IeDSP)
• Sets conditions for conditional branching command of multiplication and addition macro (USR2, USR1,
and USR0).
●
Status function
• Multiplication and addition macro current state acquisition flag (RunDSP)
• Interrupt request flag (IrqDSP)
• Saturation flag (SatDSP)
DSP-CSR
Address: 3A1
H
[bit7] SatDSP (Saturation flag): Read only
• This status flag stores whether saturation was performed during calculation.
• This bit is set if saturation is indicated in the STR command (CLP = 1), and saturation was actually
performed. If this bit is set during calculation, the setting is maintained until the next calculation starts.
• This bit is cleared when calculation begins.
Set factor: Set if the STR command performed saturation processing during calculation.
Clear factor: Cleared by start of calculation [initial value].
• At reset: Be initialized to "0". (No saturation)
• This bit is read-only. Writing does not change the bit value.
CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR
Bit 7 Bit 6 Bit 5
USR2 USR1
USR2 USR1
SatDSP
( R ) (R/W) (R/W)
0 0 0
Bit 4 Bit 3 Bit 2
USR0 IrqDSP IeDSP HltDSP
USR0 IrqDSP IeDSP
(R/W) (R/W) (R/W)
0 0 0
Bit 1 Bit 0
GoDSP Write
RunDSP Read
(W) (R/W)
Read/Write
0 0
Initial value
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