Serial Input Data Register 0 (Sidr0) And Serial Output Data Register 0 (Sodr0) - Fujitsu MB90895 Series Hardware Manual

14.3.4 Serial Input Data Register 0 (SIDR0) and Serial Output
Data Register 0 (SODR0)
The serial input data register and serial output data register are allocated to the same
address.The register functions as the serial data input register at a read; the register
functions as the serial data output register at a write.
I Serial input data register 0 (SIDR0)
R : Read only
X : Undefined
SIDR0 is a data buffer register for receiving serial data.
• The serial data signal sent to the serial input pin (SIN0) is converted by the shift register and stored in
serial input data register 0 (SIDR0).
• When the data length is 7 bits, the upper one bit (SIDR1: D7) becomes invalid.
• When received data is stored in serial input data register 0 (SIDR0), the receive data load flag bit (SSR0:
RDRF) is set to "1".When reception interrupts have been enabled (SSR0: RIE = 1), a reception interrupt
request is generated.
• Serial input data register 0 (SIDR0) should be read with the receive data load flag bit (SSR0: RDRF)
containing "1".When serial input data register 0 (SIDR0) is read, the receive data load flag (SSR0:
RDRF) is automatically cleared to "0".
• When a reception error occurs (SSR0: PE, ORE, or FRE = "1"), received data in serial input data
register 0 (SIDR0) is made invalid.
Figure 14.3-5 Serial input data register 0 (SIDR0)
bit7 6
D7 D6 D5
R R
5 4 3 2 1
D4 D3 D2 D1
R R R R R
CHAPTER 14 UART0
bit0
Reset value
D0
XXXXXXXX
B
R
395