Figure 7.10-1 Counter Operation During Subclock Or Standby Modes And Operation Halt - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 7 8/16-BIT TIMER/COUNTER

Figure 7.10-1 Counter Operation during Subclock or Standby Modes and Operation Halt

Counter value
Data register
set value
0000
Counter cleared
T1STR bit
T1IF bit
(T1IE bit)
TO pin
SLP bit
(STBC register)
STP bit
(STBC register)
T1STP bit
*: When the pin state specification bit (SPL) in the standby control register (STBC) is "1" with no pull-up resistor
option provided for the TO pin, the TO pin in stop mode enters a high impedance state.
When the SPL bit is "0", the counter holds the value that it has immediately before transition to stop mode.
186
H
Activate
Match
Cleared by program
Sleep
Sleep mode is
canceled by IRQ3.
Match Match
*
Stop
Pause
External interrupt
Time
Match Match