Interrupt Control Registers - Fujitsu MB91260B Series Hardware Manual

CHAPTER 5 INTERRUPT CONTROLLER
5.2

Interrupt Control Registers

This section describes register configuration and functions of interrupt controller.
■ Interrupt Control Register (ICR:ICR00 to ICR47)
ICR00 to ICR47
Address
000440
H
An interrupt control register (ICR) is provided for each interrupt input and is used to set the interrupt level
of the corresponding interrupt request.
[bit4 to bit0] ICR4 to ICR0
These bits are interrupt level setting bits to specify the interrupt level of the corresponding interrupt request.
If the interrupt level set in this register is higher than the level mask value set in the ILM register in the
CPU, an interrupt request is masked on the CPU side.
The register is initialized to "11111
Table 5.2-1 below lists the available combinations of values of the interrupt level setting bits and their
respective interrupt levels.
Table 5.2-1 Interrupt Level Setting Bit Values and Interrupt Levels
ICR4
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
The ICR4 bit is fixed at "1"; it cannot be set to "0".
118
Bit No. →
7 6
– –
to 00046F
H
ICR3 ICR2
0 0
1 1
1 1
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
5 4 3
– ICR4 ICR3
R R/W
" at reset.
B
ICR1 ICR0
0 0 0
1 0 14
1 1 15
0 0 16
0 1 17
1 0 18
1 1 19
0 0 20
0 1 21
1 0 22
1 1 23
0 0 24
0 1 25
1 0 26
1 1 27
0 0 28
0 1 29
1 0 30
1 1 31
2 1 0 Initial value
ICR2 ICR1 ICR0
R/W R/W R/W
Interrupt Level
System-reserved
NMI
Highest level available
(High)
(Low)
Interrupt-disabled
---11111
B