Interrupt Control Register (Icr) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 3 INTERRUPTS
3.6.1

Interrupt Control Register (ICR)

The interrupt control register is located in the interrupt controller, which corresponds
to all I/Os that support interrupt functions. The interrupt control register has the
following three functions:
• Specifying an interrupt level for the corresponding peripheral resource.
• Selecting whether the interrupts of the corresponding peripheral should be handled
as normal interrupts or by the expanded intelligent I/O service.
• Selecting a channel for the expanded intelligent I/O service.
Do not access this register with read-modify-write instructions, as this may cause a
malfunction.
■ Interrupt Control Register (ICR)
Interrupt control register (ICR)
Address:
B0 to BF
H
Read/write
Initial value
Address:
B0 to BF
H
Read/write
Initial value
Note:
ICS3 to ICS0 are effective only when the EI
2
EI OS, and to "0" otherwise. When the EI
ICS1 and ICS0 are effective only during writing, while S1 and S0 are effective only during reading.
[bit15 to bit12, bit7 to bit4] ICS3 to ICS0 (EI
The bits ICS3 to ICS0 are the channel selection bits for EI
These bits are write only and specify a channel for the EI
The value in these bits determines the address of an expended intelligent I/O service
descriptor in the memory. The ICS is initialized to "0000
70
Figure 3.6-2 Interrupt Control Register (ICR)
15/7 14/6
bit
ICS3 ICS2
H
(W) (W)
(0) (0)
15/7 14/6
bit
H
(-) (-)
(X) (X)
13/5 12/4 11/3 10/2
ICS1 ICS0 ISE IL2
(W) (W) (W) (W)
(0) (0) (0) (1)
13/5 12/4 11/3 10/2
ISE IL2
S1 S0
(R) (R) (R) (R)
(0) (0) (0) (1)
2
OS is executed. Set the ISE to "1" when executing the
2
OS is not executed, ICS3 to ICS0 may have any value.
2
OS channel selection bits)
2
" by a reset.
B
9/1
8/0
When writing
IL1 IL0
(W) (W)
(1) (1)
9/1
8/0
When reading
IL1 IL0
(R) (R)
(1) (1)
2
OS.
OS.